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1 INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic Package Outlines 74C/CT191 Presettable synchronous 4-bit binary File under Integrated Circuits, IC6 December 199

2 74C/CT191 FEATURES Synchronous reversible counting Asynchronous parallel load Count enable control for synchronous expansion Single up/down control input Output capability: standard I CC category: MSI GENERA DESCRIPTION The 74C/CT191 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TT (STT). They are specified in compliance with JEDEC standard no. 7A. The 74C/CT191 are asynchronously presettable 4-bit binary s. They contain four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation. Asynchronous parallel load capability permits the counter to be preset to any desired number. Information present on the parallel data inputs (D to D 3 ) is loaded into the counter and appears on the outputs when the parallel load (P) input is OW. As indicated in the function table, this operation overrides the counting function. Counting is inhibited by a IG level on the count enable (CE) input. When CE is OW internal state changes are initiated synchronously by the OW-to-IG transition of the clock input. The up/down (U/D) input signal determines the direction of counting as indicated in the function table. The CE input may go OW when the clock is in either state, however, the OW-to-IG CE transition must occur only when the clock is IG. Also, the U/D input should be changed only when either CE or CP is IG. Overflow/underflow indications are provided by two types of outputs, the terminal count (TC) and ripple clock (RC). The TC output is normally OW and goes IG when a circuit reaches zero in the count-down mode or reaches 15 in the count-up-mode. The TC output will remain IG until a state change occurs, either by counting or presetting, or until U/D is changed. Do not use the TC output as a clock signal because it is subject to decoding spikes. The TC signal is used internally to enable the RC output. When TC is IG and CE is OW, the RC output follows the clock pulse (CP). This feature simplifies the design of multistage counters as shown in Figs 5 and 6. In Fig.5, each RC output is used as the clock input to the next higher stage. It is only necessary to inhibit the first stage to prevent counting in all stages, since a IG on CE inhibits the RC output pulse as indicated in the function table. The timing skew between state changes in the first and last stages is represented by the cumulative delay of the clock as it ripples through the preceding stages. This can be a disadvantage of this configuration in some applications. Fig.6 shows a method of causing state changes to occur simultaneously in all stages. The RC outputs propagate the carry/borrow signals in ripple fashion and all clock inputs are driven in parallel. In this configuration the duration of the clock OW state must be long enough to allow the negative-going edge of the carry/borrow signal to ripple through to the last stage before the clock goes IG. Since the RC output of any package goes IG shortly after its CP input goes IG there is no such restriction on the IG-state duration of the clock. In Fig.7, the configuration shown avoids ripple delays and their associated restrictions. Combining the TC signals from all the preceding stages forms the CE input for a given stage. An enable must be included in each carry gate in order to inhibit counting. The TC output of a given stage it not affected by its own CE signal therefore the simple inhibit scheme of Figs 5 and 6 does not apply. December 199 2

3 74C/CT191 QUICK REFERENCE DATA GND = V; T amb =25 C; t r =t f =6ns TYPICA SYMBO PARAMETER CONDITIONS C CT UNIT t P / t P CP to Q n C = 15 pf; V CC = 5 V ns f max maximum clock frequency Mz C I input capacitance pf C PD power dissipation capacitance per package notes 1 and pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + (C V 2 CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C V 2 CC f o ) = sum of outputs C = output load capacitance in pf V CC = supply voltage in V 2. For C the condition is V I = GND to V CC For CT the condition is V I = GND to V CC 1.5 V ORDERING INFORMATION See 74C/CT/CU/CMOS ogic Package Information. December 199 3

4 74C/CT191 PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION 3, 2, 6, 7 Q to Q 3 flip-flop outputs 4 CE count enable input (active OW) 5 U/D up/down input 8 GND ground ( V) 11 P parallel load input (active OW) 12 TC terminal count output 13 RC ripple clock output (active OW) 14 CP clock input (OW-to-IG, edge triggered) 15, 1, 1, 9 D to D 3 data inputs 16 V CC positive supply voltage Fig.1 Pin configuration. Fig.2 ogic symbol. Fig.3 IEC logic symbol. December 199 4

5 74C/CT191 Fig.4 Functional diagram. FUNCTION TABE parallel load OPERATING MODE INPUTS P U/D CE CP D n Q n OUTPUTS count up I count up count down I count down hold (do nothing) no change TC AND RC FUNCTION TABE INPUTS TERMINA COUNT STATE OUTPUTS U/D CE CP Q Q 1 Q 2 Q 3 TC RC Notes 1. = IG voltage level = OW voltage level I = OW voltage level one set-up time prior to the OW-to-IG CP transition = don t care = OW-to-IG CP transition = one OW level pulse = TC goes OW on a OW-to-IG CP transition December 199 5

6 74C/CT191 Fig.5 N-stage ripple counter using ripple clock. Fig.6 Synchronous n-stage counter using ripple carry/borrow. Fig.7 Synchronous n-stage counter with parallel gated carry/borrow. December 199 6

7 74C/CT191 Sequence oad (preset) to binary thirteen; count up to fourteen, fifteen, zero, one and two; inhibit; count down to one, zero, fifteen, fourteen and thirteen. Fig.8 Typical load, count and inhibit sequence. Fig.9 ogic diagram. December 199 7

8 74C/CT191 DC CARACTERISTICS FOR 74C For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: standard I CC category: MSI AC CARACTERISTICS FOR 74C GND = V; t r =t f = 6 ns; C =5pF SYMBO t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P PARAMETER 72 CP to Q n CP to TC CP to RC CE to RC T amb ( C) 74C to to +125 min. typ. max. min. max. min. max D n to Q n P to Q n U/D to TC U/D to RC t T / t T output transition time t W t W clock pulse width IG or OW parallel load pulse width OW UNIT TEST CONDITIONS V CC (V) ns ns ns ns ns ns ns ns ns ns ns WAVEFORMS Fig.1 Fig.1 Fig.11 Fig.11 Fig.12 Fig.13 Fig.14 Fig.14 Fig.15 Fig.1 Fig.15 December 199 8

9 74C/CT191 T amb ( C) TEST CONDITIONS SYMBO PARAMETER 74C to to +125 min. typ. max. min. max. min. max. UNIT V CC (V) WAVEFORMS t rem t su t su t su t h t h t h f max removal time P to CP set-up time U/D to CP set-up time D n to P set-up time CE to CP hold time U/D to CP hold time D n to P hold time CE to CP maximum clock pulse frequency ns ns ns ns ns ns ns Mz Fig.15 Fig.17 Fig.16 Fig.17 Fig.17 Fig.16 Fig.17 Fig.1 December 199 9

10 74C/CT191 DC CARACTERISTICS FOR 74CT For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: standard I CC category: MSI Note to CT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT D n CP U/D CE, P UNIT OAD COEFFICIENT December 199 1

11 74C/CT191 AC CARACTERISTICS FOR 74CT GND = V; t r =t f = 6 ns; C = 5 pf T amb ( C) TEST CONDITIONS ns Fig.1 74C SYMBO PARAMETER UNIT V WAVEFORMS to to +125 CC (V) min. typ. max. min. max. min. max. t P / t P CP to Q n t P / t P ns Fig.1 CP to TC t P / t P ns Fig.11 CP to RC t P / t P ns Fig.11 CE to RC t P / t P ns Fig.12 D n to Q n t P / t P ns Fig.13 P to Q n t P / t P ns Fig.14 U/D to TC t P / t P ns Fig.14 U/D to RC t T / t T output transition time ns Fig.15 t W t W t rem t su t su t su t h t h t h f max clock pulse width IG or OW parallel load pulse width OW removal time P to CP set-up time U/D to CP set-up time D n to P set-up time CE to CP hold time U/D to CP hold time D n to P hold time CE to CP maximum clock pulse frequency ns Fig ns Fig ns Fig ns Fig ns Fig ns Fig ns Fig.17 5 ns Fig.16 1 ns Fig Mz Fig.1 December

12 74C/CT191 AC WAVEFORMS (1) C : V M = 5%; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Fig.1 Waveforms showing the clock (CP) to output (Q n ) s, the clock pulse width and the maximum clock pulse frequency. (1) C : V M = 5%; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Fig.11 Waveforms showing the clock and count enable inputs (CP, CE) to ripple clock output (RC) propagation delays. (1) C : V M = 5%; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Fig.12 Waveforms showing the input (D n ) to output (Q n ) s. December

13 74C/CT191 (1) C : V M = 5%; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Fig.13 Waveforms showing the input (P) to output (Q n ) s. (1) C : V M = 5%; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Fig.14 Waveforms showing the up/down count input (U/D) to terminal count and ripple clock output (TC, RC) s. (1) C : V M = 5%; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Fig.15 Waveforms showing the parallel load input (P) pulse width, removal time to clock (CP) and the output (Q n ) transition times. December

14 74C/CT191 The shaded areas indicate when the input is permitted to change for predictable output performance. (1) C : V M = 5%; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Fig.16 Waveforms showing the set-up and hold times from the parallel load input (P) to the data input (D n ). The shaded areas indicate when the input is permitted to change for predictable output performance. (1) C : V M = 5%; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Fig.17 Waveforms showing the set-up and hold times from the count enable and up/down inputs (CE, U/D) to the clock (CP). PACKAGE OUTINES See 74C/CT/CU/CMOS ogic Package Outlines. December

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