Master/Slave Flip Flops


 Buck Parrish
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1 Master/Slave Flip Flops Page 1
2 A Master/Slave Flip Flop ( Type) Gated latch(master) Gated latch (slave) 1 Gate Gate GATE Either: The master is loading (the master in on) or The slave is loading (the slave is on) But never both at the same time Page 2
3 FF Timing Gate 1 Gate GATE Master Loads Slave Loads Master Loads Slave Loads Master Loads Slave Loads Gate 1 time Page 3
4 Output Changes in Response to Falling Clock Gate 1 Gate GATE Master Loads Slave Loads Master Loads Slave Loads Master Loads Slave Loads 1 time Page 4
5 FF etailed Schematic Master latch () Usually call the gate Slave latch (SR) Page 5
6 A Falling Edge Triggered FF Edgetriggered Falling edge triggered Page 6
7 Oscillator (Toggle Circuit) Operation time Page 7
8 Rising Edge Triggered FF Schematic Edgetriggered Rising edge triggered Page 8
9 Oscillator (Toggle Circuit) Operation time Page 9
10 Flip Flop Transition Table = No clock shown since it is edge triggered (assumed) Page 10
11 Falling vs. Rising Edge Triggered fall rise fall rise Page 11
12 Alternative Flip Flops T JK Page 12
13 Toggle Flip Flop T + T T No Action Toggle + = T + T = T + Clock edge is assumed in this transition table Page 13
14 Toggle Flip Flop T + T T No Action Toggle + = T + T = T + An oscillator with an enable input (T) T Page 14
15 Toggle Flip Flop T Page 15
16 JK Flip Flop J K + J K J K No Change Reset Set Toggle Kind of a cross between a SR FF and a T FF + = K + J Page 16
17 JK Flip Flop J K Page 17
18 Why Alternative FF s? With discrete parts (TTL family) JK or T FF s could reduce gate count for the input forming logic Extensively used With VLSI IC s and FPGA s JK or T FF s must be built from FF+gates Larger, slower than a FF Not used Page 18
19 Flip Flops With Additional Control Inputs Page 19
20 What is this???? Page 20
21 What is this? Enable A falling edge triggered, type FF with enable Master only loads when =Enable= 1 Page 21
22 What is this???? Page 22
23 What is this? Set A falling edge triggered, type FF with an asynchronous set If Set=1 then =>1, regardless of or Page 23
24 What is this???? Page 24
25 What is this? Set A falling edge triggered, type FF with a synchronous set If Set=1 then =>1 on the next falling edge of the clock, regardless of Page 25
26 Flip Flops With Additional Control Inputs A variety of FF s have been made over the years They contain combinations of these inputs: Enable Set Reset The Set and Reset can be either: Asynchronous (independent of ) Synchronous (work only on edge) Page 26
27 Flip Flop Timing Characteristics Page 27
28 Clockto Time (t ) t = t NOT + t AN + 2 x t NOR Why 2 x t NOR? The output does not change instantaneously Page 28
29 t t time Page 29
30 Setup Time (t setup ) t setup = t NOT + t AN + 2 x t NOR The input has to get there early enough to set the master latch before the clock turns off Page 30
31 t setup t setup time Page 31
32 Rising Edge FF Setup Time (t SETUP ) Same setup time as before Clock is delayed through the NOT gate Page 32
33 t setupold time Page 33
34 dly t not t setupold t setupold time Page 34
35 new dly t not t setupold t setupold time Page 35
36 new dly t setup t setupold time Page 36
37 Falling Edge Hold Time (t hold ) t hold = 0ns (AN gates turn off immediately) You have to keep the old value there until the AN gates are shut off (but no longer) Page 37
38 Rising Edge Hold Time (t hold ) t hold = t NOT You have to keep the old value there until the AN gates are shut off Page 38
39 t hold t hold = t NOT Clock edge AN gate turns off, can now change time Page 39
40 Flip Flop Timing t hold t setup t time Page 40
41 Timing of a Synchronous System Input Input Forming Forming Logic Logic t CYCLE >= t + t IFL + t SETUP t t IFL t SETUP time Page 41
42 Example of a Synchronous System 4 +1 Circuit 4 4 One transition per clock edge CNT = Page 42
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