V DSS Rds(on) max I D

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1 Applications l Switch Mode Power Supply ( SMPS ) l Uninterruptable Power Supply l High speed power switching l Lead-Free Benefits l Low Gate Charge Qg results in Simple Drive Requirement l Improved Gate, Avalanche and dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche Voltage and Current l Effective Coss specified ( See AN 00) SMPS MOSFET IRF740APbF HEXFET Power MOSFET V DSS Rds(on) max I D 400V 0.55Ω 0A TO-220AB G D S PD Absolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V 0V 0 I T C = 00 C Continuous Drain Current, V 0V 6.3 A I DM Pulsed Drain Current 40 P C = 25 C Power Dissipation 25 W Linear Derating Factor.0 W/ C V GS Gate-to-Source Voltage ± 30 V dv/dt Peak Diode Recovery dv/dt ƒ 5.9 V/ns T J Operating Junction and -55 to 50 T STG Storage Temperature Range C Soldering Temperature, for 0 seconds 300 (.6mm from case ) Mounting torqe, 6-32 or M3 screw 0 lbf in (.N m) Typical SMPS Topologies: l l Single transistor Flyback Xfmr. Reset Single Transistor Forward Xfmr. Reset ( Both for US Line Input only ) Notes through are on page 8 Document Number: 905 /0/03

2 T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 400 V V GS = 0V, I D = 250µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0.48 V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance 0.55 Ω V GS = 0V, I D = 6.0A V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µA I DSS Drain-to-Source Leakage Current 25 V µa DS = 400V, V GS = 0V 250 V DS = 320V, V GS = 0V, T J = 25 C I GSS Gate-to-Source Forward Leakage 00 V GS = 30V na Gate-to-Source Reverse Leakage -00 V GS = -30V T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 4.9 S V DS = 50V, I D = 6.0A Q g Total Gate Charge 36 I D = 0A Q gs Gate-to-Source Charge 9.9 nc V DS = 320V Q gd Gate-to-Drain ("Miller") Charge 6 V GS = 0V, See Fig. 6 and 3 t d(on) Turn-On Delay Time 0 V DD = 200V t r Rise Time 35 ns I D = 0A t d(off) Turn-Off Delay Time 24 R G = 0Ω t f Fall Time 22 R D = 9.5Ω,See Fig. 0 C iss Input Capacitance 030 V GS = 0V C oss Output Capacitance 70 V DS = 25V C rss Reverse Transfer Capacitance 7.7 pf ƒ =.0MHz, See Fig. 5 C oss Output Capacitance 490 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 52 V GS = 0V, V DS = 320V, ƒ =.0MHz C oss eff. Effective Output Capacitance 6 V GS = 0V, V DS = 0V to 320V Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energy 630 mj I AR Avalanche Current 0 A E AR Repetitive Avalanche Energy 2.5 mj Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case.0 R θcs Case-to-Sink, Flat, Greased Surface 0.50 C/W R θja Junction-to-Ambient 62 Diode Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 0 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 40 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage 2.0 V T J = 25 C, I S = 0A, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 0A Q rr Reverse RecoveryCharge µc di/dt = 00A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) Document Number: 905 2

3 I D, Drain-to-Source Current (A) VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V I D, Drain-to-Source Current (A) 00 0 VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH 0.0 T J = 25 C V DS, Drain-to-Source Voltage (V) 20µs PULSE WIDTH T J = 50 C V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) 00 0 T J = 50 C T J = 25 C V DS= 50V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 3.0 I D = 0A V GS = 0V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature Document Number: 905 3

4 C, Capacitance(pF) V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss Coss Crss V DS, Drain-to-Source Voltage (V) V GS, Gate-to-Source Voltage (V) I = D 0A V DS = 320V V DS = 200V V DS = 80V FOR TEST CIRCUIT SEE FIGURE Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) 00 0 T J = 50 C T J = 25 C V GS = 0 V V SD,Source-to-Drain Voltage (V) I D, Drain Current (A) 00 0 OPERATION IN THIS AREA LIMITED BY R DS(on) 0us 00us ms TC = 25 C TJ = 50 C Single Pulse 0ms V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area Document Number: 905 4

5 0.0 V DS R D I D, Drain Current (A) Fig 0a. Switching Time Test Circuit V DS 90% R G V GS 0V Pulse Width µs Duty Factor 0. % D.U.T. - V DD T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature 0% V GS t d(on) t r t d(off) t f Fig 0b. Switching Time Waveforms 0 Thermal Response (Z thjc ) D = SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc TC t, Rectangular Pulse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case Document Number: 905 5

6 V DSav, Avalanche Voltage ( V ) IRF740APbF 5V V DS L DRIVER R G 20V D.U.T I AS - V DD A tp 0.0Ω Fig 2a. Unclamped Inductive Test Circuit V (BR)DSS tp E AS, Single Pulse Avalanche Energy (mj) TOP BOTTOM I D 4.5A 6.3A 0A Starting T, Junction Temperature ( J C) I AS Fig 2b. Unclamped Inductive Waveforms Q G Fig 2c. Maximum Avalanche Energy Vs. Drain Current 0 V Q GS Q GD 580 V G 560 Current Regulator Same Type as D.U.T. Charge Fig 3a. Basic Gate Charge Waveform KΩ 2V.2µF.3µF 500 V GS D.U.T. V - DS mA I AV, Avalanche Current ( A) I G I D Current Sampling Resistors Fig 3b. Gate Charge Test Circuit Document Number: 905 Fig 2d. Typical Drain-to-Source Voltage Vs. Avalanche Current 6

7 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =0V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For N-Channel HEXFETS Document Number: 905 7

8 TO-220AB Package Outline Dimensions are shown in millimeters (inches) 2.87 (.3) 2.62 (.03) 0.54 (.45) 0.29 (.405) 3.78 (.49) 3.54 (.39) - A (.85) 4.20 (.65) - B -.32 (.052).22 (.048) 5.24 (.600) 4.84 (.584) 4.09 (.555) 3.47 (.530) (.255) 6.0 (.240).5 (.045) MIN 4.06 (.60) 3.55 (.40) LEAD ASSIGNMENTS LEAD ASSIGNMENTS HEXFET IGBTs, CoPACK - GATE - GATE 2 - DRAIN - GATE 2- DRAIN 3 - SOURCE 2- COLLECTOR 3- SOURCE 4 - DRAIN 3- EMITTER 4- DRAIN 4- COLLECTOR 3X.40 (.055).5 (.045) 2.54 (.00) 2X NOTES: 0.93 (.037) 3X 0.69 (.027) 0.36 (.04) M B A M 3X 0.55 (.022) 0.46 (.08) 2.92 (.5) 2.64 (.04) DIMENSIONING & TOLERANCING PER ANSI Y4.5M, OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO-220AB Part Marking Information EXAMPLE: T HIS IS AN IRF00 LOT CODE 789 AS S EMBLED ON WW 9, 997 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead-Free" INT ER NAT IONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 997 WEEK 9 LINE C Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) Starting T J = 25 C, L = 2.6mH R G = 25Ω, I AS = 0A. (See Figure 2) ƒ I SD 0A, di/dt 330A/µs, V DD V (BR)DSS, T J 50 C Pulse width 300µs; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (30) TAC Fax: (30) /03 Document Number: 905 8

9 Legal Disclaimer Notice Vishay Notice The products described herein were acquired by Vishay Intertechnology, Inc., as part of its acquisition of International Rectifier s Power Control Systems (PCS) business, which closed in April Specifications of the products displayed herein are pending review by Vishay and are subject to the terms and conditions shown below. Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale. International Rectifier, IR, the IR logo, HEXFET, HEXSense, HEXDIP, DOL, INTERO, and POWIRTRAIN are registered trademarks of International Rectifier Corporation in the U.S. and other countries. All other product names noted herein may be trademarks of their respective owners. Document Number: 9990 Revision: 2-Mar-07

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