Latches and Flip-Flops

Transcription

1 Latches and Flip-Flops Objectives Explain the operation of an - latch Explain the operation of a gated - latch and a latch escribe the difference between a latch and a flip-flop Explain the operation of edge-triggered - flip-flop, flip-flop, and - flip-flop. escribe the difference between - flip-flop, - flip-flop and T flip-flop Understand the operation of a master-slave - flip-flop tudy the characteristic equation of the flip-flop Carry out the analysis of synchronous sequential systems Latches The latches and flip-flop are circuits that have two stable states and are able to remain in either one for an indefinite length of time. The circuit will change state only when a switching operation is initiated by a trigger pulse applied to the appropriate terminal. A latch is level triggered, i.e. its operation is initiated by the voltage level applied to its input and not by any change in the clock. The operation of a flip-flop is triggered by the transition of an input signal, either the leading edge (0 to1), or the trailing edge (1 to 0), of the clock waveform. The clock is a rectangular voltage pulse waveform of constant frequency. The - (set-reset) latch - latch using NO gates - latch using NAN gates When the output is HIGH, the latch is in the ET state. When the output is LOW, the latch is in the EET state. Analysis 1. et condition: = 1 and = 0 = 1 and = 0. = 0 together with = 0 also cause = 1. When = 1 is removed, the latch remember that it is et (i.e. = 1 and = 0 ). 2. Hold condition: = 0, = 0, and = 1 with previous being et. The lower NO has a 0-1 at its inputs = 0, and the upper NO has a 0-0 inputs = 1. The latch remains et even after the

2 et input was returned to eset condition: = 0 and = 1 = 0. The 0-0 inputs at the lower NO inputs = Invalid condition: = 1 and = 1 = 0 and = 0, which is the condition that is not used. Function table n+1 n+1 Comments 0 0 n n Hold (no change) et eset Invalid (not used) Logic symbol for the - latch Characteristic equation The characteristic equation of a latch describes the relationship between the new output in terms of the inputs and the current output. Characteristic equation of the - latch 1 { n + = + = n 0 Example: - timing analysis For the - latch and the and waveforms given in the following figure, sketch the output waveform that will result.

3 Function e t H o l d e s e t H o l d e t H o l d e s e t H o l d e t H o l d The gated - latch imple gate circuits, combinational logic, and transparent - latches are called asynchronous because the output responds immediately to input changes. ynchronous circuits operate sequentially with a control input. To make the - latch synchronous, we add a gated input to enable and disable the - latch into a gated - latch. Gate enable G Gated - latch Logic symbol of gated - latch When the Gate Enable is HIGH, the output of latch is controlled by the state of the and. When the Gate Enable is LOW, the latch is at hold condition. The gated latch The gated latch is formed from the gated - latch by addition of an inverter, which enables to use a single input () to both et and eset. G G Characteristic equation of the latch n+1 = n Example etermine the output waveform if the inputs shown in the following figure are applied to a gated latch, which initially eset.

4 EN olution Whenever is HIGH and EN is HIGH, goes HIGH. Whenever is LOW and EN is HIGH, goes LOW. When EN is LOW, the state of the latch is not affected by the input. Edge-triggered flip-flops An edge triggered flip-flop changes state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock pulse and is sensitive to the inputs only at this transition of the clock. A type of pulse transition detector delay pike produced by delay (when both gate inputs are HIGH) Edge-triggered - flip-flop The flip-flop cannot change state except on the triggering edge of a clock pulse. A positive edge-triggered - flip-flop Truth table for a positive edge-triggered - flip-flop n+1 n+1 Comments 0 0 X n n Hold (no change) eset et 1 1?? Invalid *X = irrelevant ( don t care ) n = output level prior to clock transition

5 Edge-triggered flip-flop The flip-flop is useful when a single data bit (1 or 0) is to be stored. A positive edge-triggered flip-flop The output of a flip-flop assumes the states of the input on the triggering edge of the clock. Truth table for a positive edge-triggered flip-flop Comments et (stores a 1) eset (stores a 0) emember, follows at the active or triggering clock edge. Example Given the waveforms in the following figure for the input and the clock, determine the output waveform if the flip-flop starts out eset. olution The output goes to the state of the input at the time of the positive-going clock edge. Edge-triggered - flip-flop The - flip-flop is a widely used type of flip-flop. The function of the - flip-flop is identical to that of the - flip-flop in the et, eset, and Hold conditions of operation. The difference is that the - flip-flop has no invalid state as does the - flip-flop. Pulse transition detector G 1 G 2 G 3 G 4 The basic internal logic for a positive edge-triggered - flip-flop

6 Assuming that the flip-flop is EET and that the and inputs are HIGH, the HIGH on the enables gate G 1, so the clock spike passes through to set the flip-flop. Now there is a HIGH on, which allows the next clock spike to pass through gate G 2 and reset the flip-flop. As you can see, on each successive clock spike, the flip-flop changes to the opposite state. This mode is called toggle operation which means that the flip-flop changes to the opposite state on each successive clock spike. acts like the input and acts like the input to an - flip-flop. With edge triggering, the flip-flop accepts data on the and inputs that are present at the active clock edge. This gives the design engineer the ability to accept input data on and at a precise time instant. Transition of the level and before or after the active clock trigger edge are ignored. positive edge negative edge Logic symbol of edge-triggered - flip-flop Truth table for a positive edge-triggered - flip-flop n+1 n+1 Comments 0 0 n n Hold (no change) eset et 1 1 n n Toggle * n = output level prior to clock transition Characteristic equation of the - flip-flop = + + n 1 n n n n Example etermine the output waveform if the, and inputs shown in the following figure are applied to a negative edge-triggered - flip-flop that is initially eset

7 olution 1. = 1, = 0 at the negative clock edge, is et. 2. = 0, = 0 at the negative clock edge, is Held. 3. = 0, = 1 at the negative clock edge, is eset. 4. = 1, = 1 at the negative clock edge, toggles. 5. = 0, = 1 at the negative clock edge, is eset. 6. = 0, = 0 at the negative clock edge, is Held. Asynchronous present and clear inputs For the flip-flops discussed, the -,, and - inputs are called synchronous inputs as the data on these inputs are transferred to the flip-flop s output only on the triggering edge of the clock pulse; that is, the data are transferred synchronously with the clock. Most integrated circuit flip-flops also have asynchronous inputs. These are inputs that affect the state of the flip-flop independent of the clock. They are normally labeled present (PE) and clear (CL). An active level on the present input will et the flip-flop, and an active level on the clear input will eset it. Logic symbol for a - flip-flop with active-low present and clear inputs PE HIGH PE CL CL Example For the positive edge-triggered - flip-flop with present and clear inputs in the following figure, determine the output for the inputs shown in the timing diagram if is initially LOW and = = PE CLE olution The resulting is shown in the figure. Present Toggle Clear

8 Master-slave - flip-flop This type of flip-flop consists of two sections, the master section and the slave section. Master lave The dashed lines are internal feedback connections that enable toggle operation Truth table for the master-slave - flip-flop n+1 n+1 Comments 0 0 n n Hold et eset 1 1 n n Toggle C Operation analysis: Gates 1 and 2 Gates 1 and 2 enabled; disabled; master loaded gates 3 and 4 enabled; slave loaded from master Cycle repeats When the dashed line is included in the analysis, with = 1 and = 1, let s assume that = 1, then the dashed feedback connection will enable gate 2, allowing the master to get eset when goes HIGH. Therefore, (of the slave) will toggle to a 0 when returns LOW Flip-flop characteristics Propagation delay time A propagation delay time is the interval of time required after an input signal has been applied for the resulting output change to occur.

9 50% point on triggering edge 50% point 50% point on HIGH-to-LOW transition of t PLH t PHL Propagation delays, clock to output PE 50% point 50% point CL 50% point 50% point t PLH t PHL Propagation delays, present input to output and clear input to output et-up time The set-up time (t s ) is the minimum interval required for the logic levels to be maintained constantly on the inputs ( and, or and, or ) prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop. 50% point 50% point t s 50% point on triggering edge t h 50% point on triggering edge Hold time The hold time (t h ) is the minimum interval required for the logic levels to remain on the inputs ( and, or and, or ) after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop. T flip-flop A T (toggle) flip-flop changes state on every tick of the clock. T

10 T flip-flop can be obtained by the use of a or - flip-flop. T T T flip-flops are most often used in counters and frequency dividers. Characteristic equation of the T flip-flop = T + + T = T n 1 n n n n n n Notice that the characteristic equation does not describe detailed timing behavior of the device (latching vs. edge-triggered, etc.), only the functional response to the control inputs. This simplified description is useful in the analysis of synchronous sequential circuits. Analysis of synchronous sequential circuits A general class of circuits in which the outputs depends on the past behavior of the circuit, as well as on the present values of inputs are called sequential circuits. In most cases a clock signal is used to control the operation of a sequential circuit; such a circuit is called a synchronous sequential circuit. ynchronous sequential circuits are also called state machines, and can be realized using combinational logic and one or more flip-flops. The general form of a sequential circuit Input Combinational circuit Flip-flops The general form of a sequential circuit Combinational circuit current state Output Example The circuit of the following diagram is a circuit with two triggering-edge triggered flip-flops. X Z

11 1. tate equation The behavior of a synchronous sequential circuit can be described by means of state equations. A state equation (also called a transition equation) specifies the next state as a function of the present state and inputs. From the circuit, we find x 1 =, 1, n+ 1 = 1n 2n + 1n = = x 2 2, n+ 1 1n z = 2n 2. tate table The time sequence of inputs, outputs, and flip-flop states can be enumerated in a state table (sometimes called a transition table). The table consists of four sections: present state, input, next state, and output. tate table 1n 2n 1,n+1 2,n+1 z x = 0 x = tate diagram A state diagram (or state graph) is a graphical representation of the behavior of the system, showing for each input combination and each state what output is and what the next state is, that is, what is to be stored in memory after the next clock. tate/output Input In the state diagram, state is represented by a circle. Also included in the circle is the output for that state. Each line coming out of a circle represents a possible transition. The label on the line indicates the input that causes that transition. There must be one path from each state for each possible input combination. This state diagram contains the identical information with the state table. tate diagram 0 00/ /1 1 01/ /0

12 tate machine structure The most general model of a sequential circuit has inputs, outputs, and internal states. It is customary to distinguish between two models of sequential circuits or state machiness: the Mealy machine and the Moore machine. They differ in the way the output is generated. A state machine whose output depends on both state and input is called a Mealy machine. In Mealy machine, the next state n+1 is a function of current state n and input, x, the output, z, is a function of current state and input. n+1 = f( n, x), z = g( n, x) Input Combinational circuit (next state logic) tate Memory (Flip-flops) Combinational circuit (Output logic) current state Output Mealy machine structure A state machine whose output depends on state alone is called a Moore machine. n+1 = f( n, x), z = g( n ) Input Combinational circuit (next state logic) tate Memory (Flip-flops) Combinational circuit (Output logic) current state Output Moore machine structure Flip-flop applications Frequency division When a pulse waveform is applied to the clock input of a - flip-flop that is connected to toggle ( = = 1), the output is a square wave with one-half the frequency of the clock input. Thus, a single flip-flop can be used as a divide-by-2 device. HIGH C Further division of a clock frequency can be achieved by using the output of one flip-flop as the clock input to a second flip-flop.

13 HIGH C A HIGH C B A B eview uestions What is the difference between a latch and a flip-flop? What levels must be placed on and to et an - latch? What is the difference between an - flip-flop and a - flip-flop? Explain why - latch is called asynchronous and the gated - flip-flop is called synchronous? What effect does a toggle operation of a - flip-flop on the output? True or false: The output will equal the level at the input at all the times. True or false: In a latch, the input can affect only when EN = 1. How does the operation of an asynchronous input differ from that of a synchronous input? Can a flip-flop respond to its and inputs while PE = 1? Which flip-flop timing parameters indicate the time it takes the output to response to an input? Exercises 1. Feed the G,, and inputs in the following figure into the gated - latch, and sketch the output wave at. EN 2. ketch the output waveform at for the inputs at and EN of the gated latch in the following figure. EN 3. raw the output relative to the clock for a flip-flop with the input as shown in the following figure. Assume positive edge-triggering and initially LOW.

14 4. For a positive edge-triggered - flip-flop with inputs as shown in the following figure, determine the output relative to the clock. Assume that starts LOW. 5. For a negative edge-triggered - flip-flop with inputs as shown in the following figure, develop the output waveform relative to the clock. Assume that is initially LOW. 6. A flip-flop is connected as shown in the following figure. etermine the output in relation to the clock. What specific function does this device perform? 7. For the following circuit with one - and one flip-flop, write the state equations and construct the state table. What type of state machine it is? Z X