# MULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question.

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1 CHAPTER3 QUESTIONS MULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question. ) If one input of an AND gate is LOW while the other is a clock signal, the output is ) A) a clock signal. B) HIGH. C) LOW. D) cannot be determined 2) Waveforms A and B represent the inputs to an OR gate. During which time interval(s) will the 2) A) time intervals 2 and 3 B) never C) time interval 4 D) time intervals 3 and 5 3) When the indicator lamp of a logic probe glows brightly, it is detecting 3) A) a HIGH logic level. B) +2 V. C) V. D) a LOW logic level. 4) Which logic circuit is represented by the Boolean equation ABC = X? 4) A) Clock B) NAND C) Inverter D) AND 5) The Boolean equation for an OR gate is. 5) A) A/B = X B) A - B = X C) AB = X D) A + B = X 6) Which logic gate is described by the following truth table? 6) A) NOR B) AND C) NAND D) OR 7) Which truth table is correct for an inverter? 7) A) B) input output input output C) input output D) input output

2 8) Waveforms A and B represent the inputs to an AND gate. During which time interval will the 8) A) time interval B) time interval 3 C) time interval 4 D) time interval 5 9) If one input of a two-input NAND gate is tied to +Vcc, the NAND functions as 9) A) an OR gate. B) an inverter. C) a NOR gate. D) an AND gate. ) What will be the output of a three-input NOR gate whose inputs are a clock, a HIGH, and a LOW? ) A) LOW B) HIGH C) clock D) cannot be determined ) In order for an AND gate to be enabled ) A) both inputs should be HIGH. B) both inputs should be LOW. C) one input should be LOW. D) one input should be HIGH. 2) In order to produce a LOW output, an OR gate requires 2) A) any input to be HIGH. B) all inputs to be LOW. C) any input to be LOW. D) all inputs to be HIGH. 3) A gate output is supposed to be HIGH. A digital probe indicator lamp is off. This could be caused by A) a nonfunctional probe. B) improper gate input. C) a failed gate. D) all of the above 3) 4) The standard logic symbols that utilize squares with symbols in them are 4) A) IEEE/IEC. B) CMOS. C) ASCII. D) ANSI. 5) A three-input NAND gate will have a HIGH output whenever 5) A) one input is HIGH. B) any two inputs are HIGH. C) one input is LOW. D) three inputs are HIGH. 6) Which logic function can be implemented by connecting an inverter to the output of a NAND gate? A) NAND B) AND C) NOR D) OR 6) 7) The Boolean equation for an AND gate is. 7) A) AB = X B) A/B = X C) A + B = X D) A - B = X 8) If one input of an OR gate is HIGH while the other is a clock signal, the output is 8) A) LOW. B) a clock signal. C) HIGH. D) cannot be determined 2

3 9) Assume that a logic gate has four inputs. How many possible input combinations will be listed in its truth table? A) 6 B) 8 C) 2 D) 4 9) 2) Which logic function is represented by the equation ABCD = X? 2) A) OR B) clock C) inverter D) AND 2) Which logic circuit is represented by the Boolean equation A + B + C + D = X? 2) A) OR B) NAND C) Inverter D) NOR 22) Which output is correct for this NAND truth table? 22)???? A) B) C) D) 23) What will be the output of a three-input NAND gate whose inputs are a HIGH, a HIGH, and a clock? A) HIGH B) a clock signal C) an inverted clock signal D) LOW 23) 24) If input A of a NAND gate is connected to a clock and input B is HIGH, the normal output is 24) A) HIGH. B) a clock signal. C) LOW. D) an inverted clock signal. 25) If one input of an OR gate is considered to be an enable, it will enable the other input when it is 25) A) the opposite of the other input. B) HIGH. C) the same as the other input. D) LOW. 26) A three-input NOR gate will have a HIGH output whenever 26) A) three inputs are LOW. B) two inputs are LOW. C) one input is HIGH. D) three inputs are HIGH. 27) Which logic gate is described by the following truth table? 27) A) OR B) NOR C) NAND D) AND 3

4 28) Waveforms A and B represent the inputs to an OR gate. During which time interval will the output from the gate (X) be LOW? 28) A) time interval B) time interval 3 C) time interval 4 D) time interval 5 29) Which logic function is represented by the equation A + B = X? 29) A) OR B) clock C) AND D) switch 3) Which output is correct for this NOR truth table? 3)???? A) B) C) D) 3) Waveforms A and B represent the inputs to a NOR gate. During which time interval(s) will the 3) A) time interval 5 B) time interval 2 C) time intervals 2, 3, and 4 D) time intervals 2 and 3 32) If input A of a NAND gate is connected to a clock and input B is LOW, the normal output is 32) A) a clock signal. B) an inverted clock signal. C) HIGH. D) LOW. 4

5 33) Which set of outputs is correct for this AND truth table? 33)???? A) B) C) D) 34) The Boolean equation for a NOR function is. 34) A) X = A + B B) X = A + B C) X = A + B D) X = A + B 35) How many inverters are in a 4-pin DIP integrated circuit? 35) A) eight B) two C) six D) four 36) In term of digital logic, a one is usually represented by 36) A) +5 V. B) V. C) + V. D) +5 V. 37) How many two-input gates are in a single 4-pin DIP integrated circuit? 37) A) two B) eight C) four D) six 38) In order for an OR gate to be enabled 38) A) both inputs should be HIGH. B) one input should be LOW. C) one input should be HIGH. D) both inputs should be LOW. 39) Which logic function can be implemented by connecting an inverter to the output of an OR gate? 39) A) NOR B) inverter C) AND D) OR 4) To pass a clock signal through a three-input OR gate 4) A) the clock must be tied to two of the inputs. B) the other inputs do not matter. C) the other inputs must be HIGH. D) the other inputs must be LOW. 4) Which logic gate is described by the following truth table? 4) A) inverter B) OR C) AND D) cannot tell 5

6 42) If one input of an OR gate is LOW while the other is a clock signal, the output is 42) A) a clock signal. B) LOW. C) HIGH. D) cannot be determined 43) Waveforms A and B represent the inputs to a NAND gate. During which time interval(s) will the 43) A) time intervals 4 and 5 B) time interval 5 C) time interval 4 D) time intervals, 2 and 3 44) Waveforms A and B represent the inputs to an AND gate. During which time interval will the 44) A) time interval B) time interval 2 C) time interval 4 D) time interval 5 45) A NAND gate with one HIGH input and one LOW input 45) A) will not function. B) functions as an AND. C) will output a LOW. D) will output a HIGH. 46) Waveforms A and B represent the inputs to an OR gate. During which time intervals will the output from the gate (X) be LOW? 46) Wa A) time intervals and 4 B) time intervals and 2 C) time intervals and 3 D) It is never low. 47) If both inputs of an AND gate are normally HIGH but one of them momentarily dips LOW, the output will A) be LOW. B) momentarily dip LOW. C) go LOW and remain LOW. D) stay HIGH. 47) 48) If one input of an AND gate is HIGH while the other is a clock signal, the output is 48) A) a clock signal. B) HIGH. C) LOW. D) cannot be determined 6

7 49) If one input of an AND gate is considered to be an enable, it will enable the other input when it is 49) A) LOW. B) HIGH. C) opposite of the other input. D) the same as the other input. 5) Which set of outputs is correct for this OR truth table? 5)???? A) B) C) D) 5) Waveforms A and B represent the inputs to a NAND gate. During which time interval(s) will the 5) A) time intervals and 2 B) time intervals, 2, 4, and 5 C) time interval 5 D) time interval 3 52) The Boolean equation for a NAND function is 52) A) X = A + B B) X = AB C) X = A B D) X = AB 53) Which logic function can be implemented by connecting an inverter to the output of a NOR gate? 53) A) NOR B) AND C) NAND D) OR 54) If input A of a NOR gate is LOW and input B is HIGH, the output should be 54) A) unknown. B) HIGH. C) changing. D) LOW. 55) The purpose of a digital pulser is to a circuit. 55) A) provide digital pulses to B) graph the output of C) float an output of D) show the logic levels of 7

8 56) Waveforms A and B represent the inputs to a NAND gate. During which time interval(s) will the output from the gate (X) be LOW? 56) A) time intervals 2, 3, and 4 B) time interval 2 C) time intervals 2 and 3 D) never 57) Inversion is indicated by 57) A) a triangle on a gate output. B) a bar (line) over a Boolean equation. C) a bubble on a gate output. D) all of the above 58) Waveforms A and B represent the inputs to a NOR gate. During which time interval(s) will the 58) A) time intervals and 2 B) time interval 3 C) time intervals, 2, 3, and 4 D) time interval 5 59) If both of its inputs are connected to the same signal, a NOR gate functions as a(n) 59) A) NOR gate. B) OR gate. C) inverter. D) AND gate. 6) A NOR gate with one HIGH input and one LOW input 6) A) will output a HIGH. B) will output a LOW. C) will not function. D) functions as an AND. 6) What is the output of a two-input NAND gate whose inputs are LOW except for narrow HIGH pulses? A) HIGH B) LOW each time a pulse occurs C) HIGH except when both inputs have a pulse at the same time D) HIGH each time a pulse occurs 6) 62) If both inputs of an OR gate are normally HIGH but one of them momentarily dips LOW, the output will A) momentarily dip LOW. B) be LOW. C) go LOW and remain LOW. D) stay HIGH. 62) 63) In terms of digital logic, a HIGH voltage usually represents 63) A) a one. B) an illegal condition. C) a zero. D) an open. 8

9 64) The truth table for a three-input OR gate contains entries. 64) A) 6 B) 3 C) 8 D) 9 65) In order to produce a HIGH output, an AND gate requires 65) A) all inputs to be LOW. B) any input to be LOW. C) all inputs to be HIGH. D) any input to be HIGH. 66) Which logic function can be implemented by connecting an inverter to the output of an AND gate? 66) A) OR B) AND C) NOR D) NAND 67) The ground and power pins on a typical TTL 4-pin DIP are 67) A) pins and 8. B) pins and 4. C) pins 7 and 4. D) pins 7 and 8. 68) When the indicator lamp of a logic probe glows dimly, it is detecting 68) A) +5 V. B) an open circuit. C) V. D) a HIGH logic level. 69) In terms of digital logic, a LOW voltage usually represents 69) A) a one. B) an open. C) an illegal condition. D) a zero. 7) Waveforms A and B represent the inputs to a NOR gate. During which time intervals will the output from the gate (X) be LOW? 7) A) all time intervals B) time intervals 2, 3, and 4 C) never D) time intervals and 5 7) In terms of digital logic, a zero is usually represented by 7) A) -5 V. B) +2 V. C) V. D) - V. 72) How many three-input NOR gates are in a 4-pin DIP integrated circuit? 72) A) five B) three C) four D) two 73) Which logic function is represented by the equation AB = X? 73) A) adder B) AND C) OR D) clock 9

10 74) Waveforms A and B represent the inputs to an AND gate. During which time intervals will output from the gate (X) be LOW? 74) A) time intervals 2 and 3 B) time intervals and 3 C) time intervals and 4 D) time intervals and 2

11 Answer Key Testname: CHAP3Q ) C 2) D 3) A 4) B 5) D 6) C 7) D 8) D 9) B ) A ) D 2) B 3) D 4) A 5) C 6) B 7) A 8) C 9) A 2) D 2) D 22) D 23) C 24) D 25) D 26) A 27) B 28) B 29) A 3) D 3) A 32) C 33) C 34) C 35) C 36) A 37) C 38) B 39) A 4) D 4) B 42) A 43) A 44) B 45) D 46) D 47) B 48) A 49) B 5) D

12 Answer Key Testname: CHAP3Q 5) B 52) B 53) D 54) D 55) A 56) B 57) D 58) D 59) C 6) B 6) C 62) D 63) A 64) C 65) C 66) D 67) C 68) B 69) D 7) B 7) C 72) B 73) B 74) B 2

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