IRFR3505PbF IRFU3505PbF HEXFET Power MOSFET

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1 Features Advanced Process Technoogy Utra Low On-Resistance 75 C Operating Temperature Fast Switching Repetitive Avaanche Aowed up to Tjmax Lead-Free Description This HEXFET Power MOSFET utiizes the atest processing techniques to achieve extremey ow on-resistance per siicon area. Additiona features of this product are a 75 C junction operating temperature, fast switching speed and improved repetitive avaanche rating. These features combine to make this design an extremey efficient and reiabe device for use in a wide variety of appications. The D-Pak is designed for surface mounting using vapor phase, infrared, or wave sodering techniques. The straight ead version (IRFU series) is for through-hoe mounting appications. Power dissipation eves up to.5 watts are possibe in typica surface mount appications. G IRFR355PbF IRFU355PbF HEXFET Power MOSFET D S D-Pak IRFR355PbF PD - 955B V DSS = 55V R DS(on) =.3Ω I D = 3A I-Pak IRFU355PbF Absoute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V V (Siicon imited) 7 I T C = C Continuous Drain Current, V V (See Fig.9) 49 A I T C = 25 C Continuous Drain Current, V V (Package imited) 3 I DM Pused Drain Current 28 P C = 25 C Power Dissipation 4 W Linear Derating Factor.92 W/ C V GS Gate-to-Source Votage ± 2 V E AS Singe Puse Avaanche Energy 2 mj E AS (tested) Singe Puse Avaanche Energy Tested Vaue 4 I AR Avaanche Current See Fig.2a, 2b, 5, 6 A E AR Repetitive Avaanche Energy mj dv/dt Peak Diode Recovery dv/dt ƒ 4. V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range C Sodering Temperature, for seconds 3 (.6mm from case ) Therma Resistance Parameter Typ. Max. Units R θjc Junction-to-Case.9 R θja Junction-to-Ambient (PCB mount)ˆ 4 C/W R θja Junction-to-Ambient 9/27/

2 IRFR/U355PbF Eectrica T J = 25 C (uness otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Votage 55 V V GS = V, I D = 25µA V (BR)DSS / T J Breakdown Votage Temp. Coefficient.57 V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance..3 Ω V GS = V, I D = 3A V GS(th) Gate Threshod Votage V V DS = V, I D = 25µA g fs Forward Transconductance 4 S V DS = 25V, I D = 3A I DSS Drain-to-Source Leakage Current 2 V µa DS = 55V, V GS = V 25 V DS = 55V, V GS = V, T J = 25 C I GSS Gate-to-Source Forward Leakage 2 V GS = 2V na Gate-to-Source Reverse Leakage -2 V GS = -2V Q g Tota Gate Charge I D = 3A Q gs Gate-to-Source Charge 7 26 nc V DS = 44V Q gd Gate-to-Drain ("Mier") Charge V GS = V t d(on) Turn-On Deay Time 3 V DD = 28V t r Rise Time 74 I D = 3A ns t d(off) Turn-Off Deay Time 43 R G = 6.8Ω t f Fa Time 54 V GS = V Between ead, D L D Interna Drain Inductance 4.5 6mm (.25in.) nh G from package L S Interna Source Inductance 7.5 and center of die contact S C iss Input Capacitance 23 V GS = V C oss Output Capacitance 47 pf V DS = 25V C rss Reverse Transfer Capacitance 9 ƒ =.MHz, See Fig. 5 C oss Output Capacitance 26 V GS = V, V DS =.V, ƒ =.MHz C oss Output Capacitance 33 V GS = V, V DS = 44V, ƒ =.MHz C oss eff. Effective Output Capacitance 63 V GS = V, V DS = V to 44V Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbo 7 (Body Diode) showing the A G I SM Pused Source Current integra reverse 28 (Body Diode) p-n junction diode. S V SD Diode Forward Votage.3 V T J = 25 C, I S = 3A, V GS = V t rr Reverse Recovery Time 7 5 ns T J = 25 C, I F = 3A, V DD = 28V Q rr Reverse RecoveryCharge 8 27 nc di/dt = A/µs t on Forward Turn-On Time Intrinsic turn-on time is negigibe (turn-on is dominated by L S L D ) Notes through ˆ are on page 2

3 I D, Drain-to-Source Current (Α) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) G fs, Forward Transconductance (S) IRFR/U355PbF V GS TOP 5V V 8.V 7.V 6.V 5.5V 5.V BOTTOM 4.5V V GS TOP 5V V 8.V 7.V 6.V 5.5V 5.V BOTTOM 4.5V 4.5V 4.5V 2µs PULSE WIDTH Tj = 25 C. V DS, Drain-to-Source Votage (V) 2µs PULSE WIDTH Tj = 75 C. V DS, Drain-to-Source Votage (V) Fig. Typica Output Characteristics Fig 2. Typica Output Characteristics 7 T J = 25 C 6 T J = 25 C T J = 75 C T J = 75 C 2 V DS = 25V 2µs PULSE WIDTH V GS, Gate-to-Source Votage (V) V DS = 25V 2µs PULSE WIDTH I D,Drain-to-Source Current (A) Fig 3. Typica Transfer Characteristics Fig 4. Typica Forward Transconductance Vs. Drain Current 3

4 I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) C, Capacitance (pf) V GS, Gate-to-Source Votage (V) IRFR/U355PbF 4 3 V GS = V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 2 6 I D = 3A V DS = 44V VDS= 28V VDS= V 2 2 Ciss 8 Coss 4 Crss V DS, Drain-to-Source Votage (V) Q G Tota Gate Charge (nc) Fig 5. Typica Capacitance Vs. Drain-to-Source Votage Fig 6. Typica Gate Charge Vs. Gate-to-Source Votage. OPERATION IN THIS AREA LIMITED BY R DS (on). T J = 75 C. µsec. T J = 25 C V GS = V V SD, Source-toDrain Votage (V) Tc = 25 C Tj = 75 C Singe Puse msec msec V DS, Drain-toSource Votage (V) Fig 7. Typica Source-Drain Diode Forward Votage Fig 8. Maximum Safe Operating Area 4

5 I D, Drain Current (A) (Normaized) IRFR/U355PbF 8 LIMITED BY PACKAGE R DS(on), Drain-to-Source On Resistance 2.5 I D = 3A V GS = V T C, Case Temperature ( C) T J, Junction Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature Fig. Normaized On-Resistance Vs. Temperature.. D = Therma Response ( Z thjc ) SINGLE PULSE ( THERMAL RESPONSE ). E-6 E t, Rectanguar Puse Duration (sec) Fig. Maximum Effective Transient Therma Impedance, Junction-to-Case 5

6 V GS(th) Gate threshod Votage (V) E AS, Singe Puse Avaanche Energy (mj) IRFR/U355PbF V DS L 5V DRIVER 4 3 TOP BOTTOM I D 2A 2A 3A R G 2V V GS tp D.U.T IAS.Ω - V DD A 2 Fig 2a. Uncamped Inductive Test Circuit tp V (BR)DSS Starting T J, Junction Temperature ( C) I AS Fig 2b. Uncamped Inductive Waveforms Q G Fig 2c. Maximum Avaanche Energy Vs. Drain Current V Q GS Q GD 4. V G 3.6 Current Reguator Same Type as D.U.T. Charge Fig 3a. Basic Gate Charge Waveform I D = 25µA 5KΩ 2V.2µF.3µF 2. V GS D.U.T. V - DS mA T J, Temperature ( C ) I G I D Current Samping Resistors Fig 3b. Gate Charge Test Circuit Fig 4. Threshod Votage Vs. Temperature 6

7 E AR, Avaanche Energy (mj) IRFR/U355PbF Duty Cyce = Singe Puse Avaanche Current (A)..5. Aowed avaanche Current vs avaanche pusewidth, tav assuming Tj = 25 C due to avaanche osses. Note: In no case shoud Tj be aowed to exceed Tjmax..E-7.E-6.E-5.E-4.E-3.E-2.E- tav (sec) Fig 5. Typica Avaanche Current Vs.Pusewidth TOP Singe Puse BOTTOM % Duty Cyce I D = 3A Starting T J, Junction Temperature ( C) Notes on Repetitive Avaanche Curves, Figures 5, 6: (For further info, see AN-5 at Avaanche faiures assumption: Purey a therma phenomenon and faiure occurs at a temperature far in excess of T jmax. This is vaidated for every part type. 2. Safe operation in Avaanche is aowed as ong ast jmax is not exceeded. 3. Equation beow based on circuit and waveforms shown in Figures 2a, 2b. 4. P D (ave) = Average power dissipation per singe avaanche puse. 5. BV = Rated breakdown votage (.3 factor accounts for votage increase during avaanche). 6. I av = Aowabe avaanche current. 7. T = Aowabe rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 5, 6). t av = Average time in avaanche. D = Duty cyce in avaanche = t av f Z thjc (D, t av ) = Transient therma resistance, see figure ) P D (ave) = /2 (.3 BV I av ) = DT/ Z thjc Fig 6. Maximum Avaanche Energy I av = 2DT/ [.3 BV Z th ] Vs. Temperature E AS (AR) = P D (ave) t av 7

8 IRFR/U355PbF - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Pane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controed by RG Driver same type as D.U.T. I SD controed by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Appied Votage Inductor Curent Body Diode Forward Drop Rippe 5% I SD * V GS = 5V for Logic Leve Devices Fig 7. Peak Diode Recovery dv/dt Test Circuit for N-Channe HEXFET Power MOSFETs V DS R D R G V GS D.U.T. - V DD V Puse Width µs Duty Factor. % Fig 8a. Switching Time Test Circuit V DS 9% % V GS t d(on) t r t d(off) t f Fig 8b. Switching Time Waveforms 8

9 IRFR/U355PbF D-Pak (TO-252AA) Package Outine Dimensions are shown in miimeters (inches) D-Pak (TO-252AA) Part Marking Information EXAMPLE: THIS IS AN IRFR2 WITH ASSEMBLY LOT CODE 234 AS SEMBLED ON WW 6, 2 IN THE ASSEMBLY LINE "A" Note: "P" in assemby ine position indicates "Lead-Free" "P" in assemby ine position indicates "Lead-F ree" quaification to the cons umer-eve INTERNATIONAL RECTIFIER LOGO AS S E MBLY LOT CODE IRFR2 6A 2 34 PART NUMBER DATE CODE YEAR = 2 WEEK 6 LINE A OR INTERNATIONAL RECTIFIER LOGO AS S EMBL Y LOT CODE IRFR PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) P = DESIGNATES LEAD-FREE PRODUCT QUALIFIED TO THE CONSUMER LEVEL (OPTIONAL) YEAR = 2 WEEK 6 A = ASSEMBLY SITE CODE Notes:. For an Automotive Quaified version of this part pease seehttp:// 2. For the most current drawing pease refer to IR website at 9

10 IRFR/U355PbF I-Pak (TO-25AA) Package Outine Dimensions are shown in miimeters (inches) I-Pak (TO-25AA) Part Marking Information EXAMPLE: THIS IS AN IRFU2 WITH ASSEMBLY LOT CODE 5678 ASSEMBLED ON WW 9, 2 IN THE ASSEMBLY LINE "A" Note: "P" in assemby ine position indicates Lead-Free" INTERNATIONAL RECTIFIER LOGO AS S EMBL Y LOT CODE IRFU2 9A PART NUMBER DATE CODE YEAR = 2 WEEK 9 LINE A OR INT ERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR = 2 WEEK 9 A = ASSEMBLY SITE CODE Notes:. For an Automotive Quaified version of this part pease seehttp:// 2. For the most current drawing pease refer to IR website at

11 D-Pak (TO-252AA) Tape & Ree Information Dimensions are shown in miimeters (inches) IRFR/U355PbF TR TRR TRL 6.3 (.64 ) 5.7 (.69 ) 6.3 (.64 ) 5.7 (.69 ) 2. (.476 ).9 (.469 ) FEED DIRECTION 8. (.38 ) 7.9 (.32 ) FEED DIRECTION NOTES :. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-48 & EIA INCH NOTES :. OUTLINE CONFORMS TO EIA mm Notes: Repetitive rating; puse width imited by max. junction temperature. (See fig. ). Limited by T Jmax, starting T J = 25 C, L =.47mH R G = 25Ω, I AS = 3A, V GS =V. Part not recommended for use above this vaue. ƒ I SD 3A, di/dt 3A/µs, V DD V (BR)DSS, T J 75 C Puse width.ms; duty cyce 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss whie V DS is rising from to 8% V DSS. Limited by T Jmax, see Fig.2a, 2b, 5, 6 for typica repetitive avaanche performance. This vaue determined from sampe faiure popuation. % tested to this vaue in production. ˆ When mounted on " square PCB (FR-4 or G- Materia). For recommended footprint and sodering techniques refer to appication note #AN-994 Data and specifications subject to change without notice. This product has been designed and quaified for the Industria market. Quaification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., E Segundo, Caifornia 9245, USA Te: (3) TAC Fax: (3) Visit us at for saes contact information.9/2