Chapter 12 Register and Counters

Transcription

1 Chapter 12 Register and Counters Lecturer: 吳安宇 Date:2006/12/8 Version: 1.0 ACCESS IC LAB

2 Outline 12.1 Register and Register Transfers 12.2 Shift Register 12.3 Design of Binary Counters 12.4 Counters for Other Sequences Counter Design Using D Flip-Flops 12.5 Counter Design Using S-R and J-K 12.6 Derivation of Flip-Flop Input Equations pp. 2

3 4bit D Flip-Flop Flop Registers pp. 3

4 Data Transfer Between Registers pp. 4

5 Use of Registers(1/2) Logic Diagram for 8-bit Register with Tri-State Output. pp. 5

6 Use of Registers(2/2) LdH If EF = 00, A is stored in G (or H). If EF = 01, B is stored in G (or H). If EF = 10, C is stored in G (or H). If EF = 11, D is stored in G (or H). pp. 6

7 N-Bit Parallel Adder with Accumulator 4-bit Register/Accumulator 4-bit Adder pp. 7

8 Adder Cell with Mux A design example for modular design Suitable for Verilog sub-circuit design module pp. 8

9 Outline 12.1 Register and Register Transfers 12.2 Shift Register 12.3 Design of Binary Counters 12.4 Counters for Other Sequences Counter Design Using D Flip-Flops 12.5 Counter Design Using S-R and J-K 12.6 Derivation of Flip-Flop Input Equations pp. 9

10 Shift Registers Initial: Q3Q2Q1Q0 = 0101 SI = 1,1,0,1 Data In Register States: pp. 10

11 Application For the purpose Delay of 7 clock Cycles Buffer of data pp. 11

12 Parallel-in,Parallel-out (PIPO) Right Shift Register Inputs Sh (Shift) L (Load) X Next State Q 3+ Q 2+ Q 1+ Q + 0 Q 3 Q 2 Q 1 Q 0 D 3 D 2 D 1 D 0 SI Q 3 Q 2 Q 1 Action No change Load Right shift D 3 D 2 D 1 D 0 = 1011 pp. 12

13 Timing Diagram D 3 D 2 D 1 D 0 = 1011 pp. 13

14 Shift Register with Inverted Feedback Start pp. 14

15 Outline 12.1 Register and Register Transfers 12.2 Shift Register 12.3 Design of Binary Counters 12.4 Counters for Other Sequences Counter Design Using D Flip-Flops 12.5 Counter Design Using S-R and J-K 12.6 Derivation of Flip-Flop Input Equations pp. 15

16 State Table Use T F/F (1/2) Present State C B A Next State C + B + A + Flip-Flop Inputs T C T B T A As Function of (A,B,C)! pp. 16

17 Using T F/F (2/2) K-map T C = AB T B = A Implement pp. 17

18 State Table Use D F/F (1/2) Present State C B A Next State C + B + A + Flip-Flop Inputs D C D B D A As Function of (A,B,C)! pp. 18

19 Using D F/F (2/2) K-map = C AB = A B = A Circuit Implement pp. 19

20 Up-down Counter U = 1, D = 0 Up Counter U = 0, D = 1 Down Counter CBA C + B + A + U D pp. 20

21 Up-down Counter The up-down can be implemented using D flip-flops and gates, as shown in Figure The corresponding logic equations are + D = A = A ( U + D) D D A B C = B = C = B ( UA + DA) = C ( UBA + DB' A') When U=1 and D=0, these equations reduce to equations for a binary up counter(equations(12-2)). When U=0 and D=1, these equations reduce to D D D A B C = = A B = C = A 1 = = B A' + = C B' A' + A' (A changes state every clock cycle) (B changes state when A = (C changes state when B = 0) A = 0) pp. 21

22 Up-down Counter D A = A + = A ( U + D ) D B = B + = B ( UA + DA ) D C = C + = C ( UBA + DB A ) pp. 22

23 Outline 12.1 Register and Register Transfers 12.2 Shift Register 12.3 Design of Binary Counters 12.4 Counters for Other Sequences Counter Design Using D Flip-Flops 12.5 Counter Design Using S-R and J-K 12.6 Derivation of Flip-Flop Input Equations pp. 23

24 State Diagram of a Counter C B A C + B + A + T C T B T A pp. 24

25 K-map Derivation Q Q T T = Q + Q pp. 25

26 Logic Network pp. 26

27 Timing Diagram of Counter Negative-edge triggered counter (3-bits). pp. 27

28 IF. IF F/F s are initially set to A=0, B=0, C=1. Tracking signals through the network shows that T A =T B =1, so the state changes to 111. When the power-on, the states of all F/F s are unpredictable Don t care states should be checked to make sure that they eventually lead into the main counting sequence or use power-on reset. pp. 28

29 c.f. Shift Register with Inverted Feedback Start pp. 29

30 Outline 12.1 Register and Register Transfers 12.2 Shift Register 12.3 Design of Binary Counters 12.4 Counters for Other Sequences Counter Design Using D Flip-Flops 12.5 Counter Design Using S-R and J-K 12.6 Derivation of Flip-Flop Input Equations pp. 30

31 State Diagram of a Counter C B A C + B + A + D C D B D A pp. 31

32 Counter Design Using D Flip-Flops Flops D C = C + = B D B = B + = C + BA D A = A + = CA + BA = A ( C + B ) pp. 32

33 Outline 12.1 Register and Register Transfers 12.2 Shift Register 12.3 Design of Binary Counters 12.4 Counters for Other Sequences Counter Design Using D Flip-Flops 12.5 Counter Design Using S-R and J-K 12.6 Derivation of Flip-Flop Input Equations pp. 33

34 Using S-R S R F/F for Counter S-R flip-flop inputs pp. 34

35 Using S-R S R F/F C B A pp. 35

36 Using S-RS From setup table pp. 36

37 Using J-KJ J-K flip-flop inputs Graduate Institute of Electronics Engineering, NTU Set J,k JK Excitation Table pp. 37

38 Using J-KJ pp. 38

39 Implementation of JK-based Counter pp. 39

40 Outline 12.1 Register and Register Transfers 12.2 Shift Register 12.3 Design of Binary Counters 12.4 Counters for Other Sequences Counter Design Using D Flip-Flops 12.5 Counter Design Using S-R and J-K 12.6 Derivation of Flip-Flop Input Equations pp. 40

41 Derivation of Flip-Flop Flop Input Equations Determine the F/F input equations from the Next-State Equations pp. 41

42 Important Tables Q Q + D Q Q + T Q Q + S R Q Q + J K X X X X X X 0 For Low-cost implement pp. 42

43 Example: Table 12-9 Input: A,B,Q pp. 43

44 Derivation of Flip-Flop Flop Input Equations Using 4-4 Variable Maps Q1 (T F/F) Q2 (SR F/F) Q3 (JK F/F) pp. 44

45 Pre-settable Counter pp. 45

46 Ld = Load Ct = Count ClrN = Clear Pre-settable Counter Ld pp. 46

47 Summary For a counter of N states, we need Log_2(N) flipflops (F/F) to record the state. Watch for Excitation equations for T F/F, SR F/F, and JK F/F in your derivation. Usually, JF F/F leads to low-cost implementations (but with more efforts). Watch for unknown states in the operations of the counter. Usually, we need to preset/reset the states for normal operations. pp. 47