Napier University. School of Engineering. Electronic Engineering A Module: SE42205 Digital Design

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1 Napier University School of Engineering Digital Design Clock + U1 out 5V "1" "2" "4" JK-FF D JK-FF C JK-FF B U8 SN7408 signal U4 SN74107 U5 SN74107 U6 SN74107 U3 SN7408 U2 J Q J Q & J Q & K CQ K CQ K CQ U9 SN7408 & "8" JK-FF A U7 SN74107 J Q + K CQ 5V By Klaus Jørgensen Napier No: Lecturer Professor A. Almaini

2 Klaus Jørgensen Page 2 of 12 Abstract This paper is about a 16 bit binary counter made by JK-Flip-Flops, and one way how to display the number of 1 the counter counts in a 16 bit binary vector, there is also a state transition diagram, state table, karnaugh maps, test of the circuit in this paper.

3 Klaus Jørgensen Page 3 of 12 Table of Contents Table of Contents...3 Introduction...4 Input Signal...5 Counter...6 State Transition Diagram...6 State table of synchronous counter...7 Karnaugh maps...8 Circuit...9 Test...9 Display...10 Conclusion...11 Reference...12

4 Klaus Jørgensen Page 4 of 12 Introduction The counter has to count the numbers of ones 1 in a 16 bit binary vector, but all the 16 digits cannot all be 1 or 0 so the maximum number of 1 can only be 15 and the minimum number of 1 can only be 1. Input Counter Display Figure 1 Figure 1 shows a block diagram of the circuit the input signal is going to be made up by a clock signal and the signal that has to be counted 1 in. The counter is going to be made by 4 JK-Flip-Flops and some gates. The display is going to be made by 7-segments.

5 Klaus Jørgensen Page 5 of 12 Input Signal The input signal is a 16 digits binary vector, but it can not be all 1 or 0 there has to be some variation in the signal, to get an output that it is possible to count, the input signal has to be broken up to smaller pulses this can be don as shown in figure 2, each 1 in the input signal has a length of 1µs, to divide the input signal in to smaller piece it is anted together with a clock signal of 1MHz where each pulse has a length of 1µs. 1 1 = pt = 1μs f 1M The output of the And gate (U3) is shown in figure 2. U1 Clock U2 Input U3 SN7408 & Output Figure 2 The input signal is a 16 digits binary vector. Input = Output = 8 1 T 5.00 Clock Input Output m u 10.00u 15.00u 20.00u Time (s) Figure 3

6 Klaus Jørgensen Page 6 of 12 Counter The 16 bit synchronous counter is made by 4 JK flip-flops and 2 gates, one JK flip-flop for each output, QA is the MSB (Most Significant Bit) and QD is the LSB (Least Significant Bit). Figure 4 shows a chart of how the JK flip-flop works. Q is the Present state, Q+ is the Next state, J and K is the inputs of the flipflop, to get from Q to Q+, J and K have to get the value as shown in figure 4 the x is a don t care state is can be 1 or 0 it doesn t matter [1]. Q Q+ J K X X 1 0 X X 0 Figure 4 [1] State Transition Diagram To get a view of how the counter must work a State Transition diagram is made, it showed in figure Figure 5

7 Klaus Jørgensen Page 7 of 12 State table of synchronous counter Figure 6 shows the State table for the counter, it shows the Present, Next and the Change state of the counter. Present State. Next State. Change State. QA QB QC QD QA+ QB+ QC+ QD+ JA KA JB KB JC KC JD KD x 0 x 0 x 1 x x 0 x 1 x x x 0 x x 0 1 x x 1 x x 1 x x x 0 0 x 1 x x x 0 1 x x x x 0 x 0 1 x x x 1 x 1 x x 0 0 x 0 x 1 x x 0 0 x 1 x x x 0 0 x x 0 1 x x 0 1 x x 1 x x 0 x 0 0 x 1 x x 0 x 0 1 x x x 0 x 0 x 0 1 x x 1 x 1 x 1 x 1 Figure 6

8 Klaus Jørgensen Page 8 of 12 Karnaugh maps The karnaugh maps and the boolean algebra expression is shown below. JA KA QDQC\ QBQA QDQC\ QBQA x x 0 0 x x x x 0 1 x x x x x 0 1 x x x 1 0 x x 0 0 JA = QBQCQD KA = QBQCQD JB KB QDQC\ QBQA QDQC\ QBQA x x x 0 0 x x x x 0 0 x x x 1 1 x x x x x 0 0 x JB = QCQD KB = QCQD JC KC QDQC\ QBQA QDQC\ QBQA x x x x 0 1 x x x x x x x x x x x x JC = QD KC = QD JD KD QDQC\ QBQA QDQC\ QBQA x x x x x x x x 1 1 x x x x x x x x JD = 1 KD = 1

9 Klaus Jørgensen Page 9 of 12 Circuit To make the counter there are used 4 JK Flip-Flops and 3 And-gates which is shown in figure 7. Clock + U1 out 5V "1" "2" "4" JK-FF D JK-FF C JK-FF B U8 SN7408 signal U4 SN74107 U5 SN74107 U6 SN74107 U3 SN7408 U2 J Q J Q & J Q & K CQ K CQ K CQ U9 SN7408 & "8" JK-FF A U7 SN74107 J Q + K CQ 5V Figure 7 Test Figure 8 shows a test of the circuit in figure 7 with the input signal which have eight 1 in it, this is shown in figure 8. T "1" m "2" m "4" m "8" m Clock out m signal u 10.00u 15.00u 20.00u Time (s) Figure 8

10 Klaus Jørgensen Page 10 of 12 Display As display it is chosen to use two 7-segment displays this are setup as shown in figure 9. but to get the display to show a value above 9 the counter has to be rest when it reach the value 9 to begin to count from one again, U14, U15 and U16 gives a high out 1 when the U12 (7-segment) gets to 10, and at the same time U18 reset the counter to count from one again, U17 is a latches, it keeps the A input on U11 high 1 so that U13 shows one until the hole circuit is reset. Figure 9

11 Klaus Jørgensen Page 11 of 12 Conclusion The counter is made by 4 JK flip-flops and 2 And-gates, and this gives a 16-bit synchronous counter, the counter could have been made by only 4 JK flipflops if there wars used a 16-bit asynchronous counter, but the asynchronous counter has some disadvantages, the flip-flops in a asynchronous counter are not clocked at the same time, they are usually clocked by the output from the precedent flip-flop, the first flip-flop in the circuit is clocked by a external event, this means that the flip-flops in a asynchronous counter do not changes the output at the same time as it happens in a synchronous counter. The asynchronous counter is also slower then the synchronous counter because the delay from each flip-flop are added together to give the totally delay, hence, the more flip-flops there are used in a circuit or the more bits the counter has to count the slower the circuit will be. If the asynchronous counter are used in a large complex system, and there are happening a lot on each clock pulse there are a good possibility for an error because some IC s are faster then other and combined with the delay from the flip-flops, there is a possibility that some of the IC s will respond before others and this will give an error in the circuit. 24/11/2005 Klaus Jørgensen

12 Klaus Jørgensen Page 12 of 12 Reference 1. Digital teknik, by Leif Møller Andersen, (A Danish book). ISBN:

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