Testing Digital Systems I
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1 Testing igital Systems I Testing igital Systems I Lecture : Test Generation for Sequential Circuits Instructor: M. Tahoori Copyright 2, M. Tahoori TS I: Lecture Sequential Circuits Approach Convert Finite State Machine to Corresponding Iterative Network Multiple Time Frames (Iterative Cells) Needed for Justification and Propagation One Fault in Sequential Circuit Many Faults in Corresponding Iterative Network Use 9-valued signals Issues Order of Justification and Propagation Simulation Values Test Point Insertion ( Partial Scan) Copyright 2, M. Tahoori TS I: Lecture 2 Lecture
2 Testing igital Systems I Sequential ATPG ifficulties Initialization of the bistables Gated clocks Circuits with multiple clock domains Internally derived clocks, mixed data and clock signals Asynchronous logic Circuits with combinational feedback paths Embedded counters Embedded RAMs and ROMs Copyright 2, M. Tahoori TS I: Lecture 3 Finite State Machine Example : serial adder S i = a i b i c i- C i = a i b i c i- (a i b i ) a b C P Q C OR S CK Copyright 2, M. Tahoori TS I: Lecture 4 Lecture 2
3 Testing igital Systems I Example Corresponding parallel binary adder circuit Iterative network of the previous circuit a b a b a2 b2 Cin P P P2 OR S OR S OR S2 C2 Copyright 2, M. Tahoori TS I: Lecture 5 General Case Huffman model of sequential circuit with edge-triggered -flip-flops x y Combinational Logic Q C CK Copyright 2, M. Tahoori TS I: Lecture 6 Lecture 3
4 Testing igital Systems I General Case Any sequential circuit with edge-triggered -FF can be directly converted into an iterative network x x xr y y yr Combinational Logic Combinational Logic Combinational Logic r Copyright 2, M. Tahoori TS I: Lecture 7 Iterative Logic Array Expansion To detect a fault, a sequence of vectors may be needed Copyright 2, M. Tahoori TS I: Lecture 8 Lecture 4
5 Testing igital Systems I Example Test for P SA Provoke Fault on P: a =, b = Propagate Fault to S2: C = Need to consider last time frame: : a =, b =, Cin = a2 =, b2 = a b a b a2 b2 Cin OR S P P P2 C C OR OR S S2 C2 Copyright 2, M. Tahoori TS I: Lecture 9 Example Test for u SA In time frame t provoke fault: u = propagate fault effect to (path E,H,): v = and G = Justify B = C = : y = and w = Requires G = in the time frame t- for a don t care value of y (i.e., y = or ) in the time frame t - u v w A y B C E Q C Copyright 2, M. Tahoori TS I: Lecture G H CK Lecture 5
6 Testing igital Systems I Example (cont) Test for u SA In time frame t - G =, y = A = U = A = in the faulty circuit Conflict! u v w A y B C E Q C Copyright 2, M. Tahoori TS I: Lecture G H CK Example (cont) Problem with this example Try to extend -algorithm for sequential circuits is in the presence of u/ irrespective of the logic values on other signal lines, and the content of the flip-flop Copyright 2, M. Tahoori TS I: Lecture 2 Lecture 6
7 Testing igital Systems I Example (cont) Input sequence to set to in the fault-free circuit E = and G = B = y = u = v = and w = in cycle t - u =, v = and w = in cycle t u v w A y B C E G H Q C CK Copyright 2, M. Tahoori TS I: Lecture 3 Nine-Valued Signals A fault can be detected even if in the presence of the fault a signal line in the faulty circuit has an unknown value () While the corresponding signal line in the fault-free circuit has a known value ( or ) or vice-versa This information is not expressed by the logic values,, and introduced in the context of the -algorithm Copyright 2, M. Tahoori TS I: Lecture 4 Lecture 7
8 Testing igital Systems I Nine-Valued Signals Symbol Symbol Fault-free circuit value Faulty Circuit Value <, > <, > <, > <, > <, > or or <, > G or <, > G or <, > F or <, > or Copyright 2, M. Tahoori TS I: Lecture 5 Using Nine-valued Signals Propagate assigned values Assign values to propagate or Assign values to provoke or at stuck fault gate output Primitive -cube of the fault Line Justification Copyright 2, M. Tahoori TS I: Lecture 6 Lecture 8
9 Testing igital Systems I Propagating Assigned Values NOT AN G G F G G F G G F G G F G G F F F F G G G F G G F G G G G G G G G G G F F F F F F F F G F Copyright 2, M. Tahoori TS I: Lecture 7 Propagation -Cubes For propagating the fault effect through an OR gate with input, apply <, > to the other inputs of the OR gate. For propagating the fault effect through an OR gate with input, apply <, > to the other inputs of the OR gate. For propagating the fault effect through an AN gate with input, apply <, > to the other inputs of the AN gate. For propagating the fault effect through an AN gate with input, apply <, > to the other inputs of the AN gate. Copyright 2, M. Tahoori TS I: Lecture 8 Lecture 9
10 Testing igital Systems I Assigning Values To Provoke Or At stuck fault gate output Primitive -cube of the fault AN Gate with output SA AN Gate with output SA a b a b <,> <,> <,> <,> <,> <,> AN Gate with input a SA AN Gate with input a SA a b a b <,> <,> <,> <,> Copyright 2, M. Tahoori TS I: Lecture 9 Line Justification AN Gate with output <,> AN Gate with output <,> a b a b <,> <,> <,> <,> <,> <,> <,> <,> <,> Copyright 2, M. Tahoori TS I: Lecture 2 Lecture
11 Testing igital Systems I Example: u/ Provoke the fault Apply <, > = on signal line u at time frame t Propagate fault effect (along path through E and H to ) v and G must be <, > = G v is a primary input v = <, > at time t A = <, > justify B = C = <, > (= G) justifying C = <, > w = C= <,> at time frame t justifying B = <, > justify y = <, > justify G = <, > at time frame t- u v w A y B C E Copyright 2, M. Tahoori TS I: Lecture 2 G H Q C CK Example: u/ (cont) justifying G = <, > (= G) in time frame t- justify B = C = <, > at time frame t- justify C = <, > by setting w = in time frame t- justifying <, > on B set A = <, > and y = <, > A = <, > u = <, > and v = <, > in time frame t- u = v = at time frame t- Test for u/ u =, v = and w = in time frame t- u =, v = and w = in time frame t u v w A y B C E Copyright 2, M. Tahoori TS I: Lecture 22 G H Q C CK Lecture
12 Testing igital Systems I Complexity of ATPG Synchronous circuit All flip-flops controlled by clocks; PI and PO synchronized with clock: Cycle-free circuit No feedback among flip-flops Test generation for a fault needs no more than dseq time-frames dseq is the sequential depth. Cyclic circuit Contains feedback among flip-flops: May need 9 Nff time-frames Nff is the number of flip-flops. Asynchronous circuit Higher complexity! Smax Time- Frame max- Time- Frame max-2 S3 Time- Frame -2 S2 Time- Frame - S Time- Frame S max = Number of distinct vectors with 9-valued elements = 9 Nff Copyright 2, M. Tahoori TS I: Lecture 23 Cycle-Free Circuits Characterized by Absence of cycles among flip-flops and a sequential depth, dseq. dseq is the maximum number of flip-flops on any path between PI and PO. Both good and faulty circuits are initializable. Test sequence length for a fault is bounded by dseq. Copyright 2, M. Tahoori TS I: Lecture 24 Lecture 2
13 Testing igital Systems I Circuit Cycle-Free Example F2 2 Level = F2 F3 3 s - graph 2 F3 Level = 3 All faults are testable dseq = 3 Copyright 2, M. Tahoori TS I: Lecture 25 Cyclic Circuit Example Modulo-3 counter CNT F2 s - graph F2 Copyright 2, M. Tahoori TS I: Lecture 26 Lecture 3
14 Testing igital Systems I Modulo-3 Counter Cyclic structure Sequential depth is undefined. Circuit is not initializable. No tests can be generated for any stuck-at fault. After expanding the circuit to 9 Nff = 8, or fewer, timeframes ATPG program calls any given target fault untestable. Circuit can only be functionally tested by multiple observations. Functional tests, when simulated, give no fault coverage. Copyright 2, M. Tahoori TS I: Lecture 27 Summary Combinational ATPG algorithms are extended: Time-frame expansion unrolls time as combinational array Nine-valued logic system Justification via backward time Cycle-free circuits: Require at most dseq time-frames dseq is the maximum number of flip-flops on any path between PI and PO Always initializable Cyclic circuits: May need 9 Nff time-frames Nff is the number of flip-flops Circuit must be initializable Partial scan can make circuit cycle-free Asynchronous circuits: High complexity Low coverage and unreliable tests Copyright 2, M. Tahoori TS I: Lecture 28 Lecture 4
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