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1 Experiment No. 1. THE DIGI DESIGNER Experiment 1-1. Socket Connections on the Digi Designer Experiment No. 2. LOGIC LEVELS AND THE 7400 QUADRUPLE 2-INPUT POSITIVE NAND GATE Experiment 2-1. Truth Table for a 2-input Positive NAND Gate Experiment 2-2. Construction of an Inverter Experiment 2-3. What Happens if I Forget to Wire Up an Input Pin to a NAND Gate? Experiment 2-4. Inverting a Clock Output Experiment 2-5. What Happens When I Cionnect Both the Normal and Inverted Clock Outputs to a 2-Input NAND Gate? Experiment No. 3. BINARY CODED DECIMAL (BCD), THE 7447 BCD-TO-SEVEN-SEGMENT DECODER/DRIVER,AND THE SEVEN-SEGMENT LED DISPLAY Experiment 3-1. Binary Coded Decimal Using Logic Switches and Lamp Monitors Experiment 3-2. Binary-Coded Decimal using Logicv Switches, the 7447 BCD-to-seven Segment Decoder/Driver, and the Seven-segment LED Display Experiment 3-3,. Truth Table for a Seven-segment LED Display Experiment 3-4. Whatr do we mean by a Lamp Test, Blanking Input, Ripple-blanking Input, and Ripple-blanking Output on the 7447 Integrated Circuit Chip? Experiment 3-5. Behold the Decimal Point on a Seven-segment LED Display! Experiment 3-7. Construction of a Binary Counter using a Seven-segment LED Display Experiment No. 4. THE 7490 DECADE COUNTER Experiment 4-1. A Decade Counter Experiment 4-2. Divide-by-two, Divide-by-five, and Divide-by-ten Counters Experiment 4-3. What do the Reset Inputs do? Experiment 4-4. Construction of Several Different Types of Counters Experiment 4-5,. When does the Count Change, on the Leading Edge or the Trailing Edge of the Clock Pulse? Experiment 4-6. Counting bounces on Mechanical Switches Experiment No. 5. THE 7476 DUAL J-K MASTER-SLAVE FLIP-FLOP WITH PRESET AND CLEAR Experiment 5-1. A Working Flip-Flop Experiment 5-2. What do the J-K Inputs Do? Experiment 5-3. What do the Clear and Preset Inputs Do? Experiment 5-4. Truth Table for a J-K Master-Slave Flip-flop Experiment 5-5. When does the Flip-flop State Change, on the Leading Edge or the Trailing Edge of the Clock Pulse? Experiment 5-6. Divide-by-two and Divide-by-four circuits using a Pair of Flip-Flops Experiment No 6. DIGITAL GATES Experiment 6-1. Truth Table for a 2-Input Positive NAND Gate Experiment 6-2. Truth Table for a 3-Input Positive NAND Gate Experiment 6-3. Truth Table for a 4-Input Positive NAND Gate Experiment 6-4. Truth Table for an 8-Input Positive NAND Gate Experiment 6-5. Truth Table for an Inverter Copyright Peter R. Rony All rights reserved.
2 Experiment 6-6. Truth Table for a 2-Input Positive NOR Gate Experiment 6-7. Truth Table for a 3-Input Positive AND Gate Experiment 6-8. Truth Table for a 2-wide, 2-Input AND-OR-INVERT Gate Experiment No. 7. PARALLEL AND SERIAL DATA TRANSMISSION AND THE BIT SHIFT REGISTER Experiment 7-1. Serial Entry of Data into an 8-Bit Shift Register Experiment 7-2. A Circulating 8-Bit Shift Register Experiment 7-3. A Serial Transmitter and Serial Receiver Experiment 7-4. A Parallel Transmitter and Parallel Receiver Experiment No. 8. OCTAL AND DECIMAL DECODERS Experiment 8-1. Truth Table for a Simple BCD-to-Decimal Decoder Experiment 8-2. A Decade Sequencer Experiment 8-3. A Decimal Decoder Experiment No. 9. DATA SELECTOR/MULTIPLEXERS Experiment 9-1. Truth Table for an 8-Line-to-1-Line Data Selector/Multiplexer Experiment 9-2. An Eight-line, 4-Biot Binary-Word Data Selector/Multiplexer Experiment 9-3. What Do Those Little Open Circles at Pins 6 and 7 in Figure 9-2 Mean? Experiment 9=4. Truth Table for a 16-Line-to-1-Line Data Selector/Multiplexer Experiment No. 10. CONSTRUCTION OF A MULTIPLEXER THAT CONVERTS BCD TO SERIAL ASCII CHARACTERS Experiment Characteristics of the Synchronous 4-Bit Binary Up/Down Counter with Preset Inputs Experiment Construction of a Synchronous Binary Down Counter that Counts from Decimal Eleven to Decimal Zero and Stops Experiment Construction of a Multiplexer that Converts BCD to Serial ASCII Characters Experiment No. 11. RANDOM ACCESS MEMORIES (RAMs) Experiment The 7493 Four-Bit Binary Counter Experiment Memory in a Minicomputer: the 64-Bit RAM Appendix: PIN CONFIGURATIONS OF 7400-SERIES INTEGRATED-CIRCUIT CHIPS Copyright Peter R. Rony All rights reserved.
3 Experiments in Digital Electronics pages 2-10.max
4 Experiments in Digital Electronics pages 2-10.max
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DATA SHEETS DE COMPONENTES DA FAMÍLIA LÓGICA TTL GATES AND INVERTERS POSITIVES NAND GATES AND INVERTERS DESCRIÇÃO
GATES AND INVERTERS POSITIVES NAND GATES AND INVERTERS Hex Invertes 74LS04 Quadruple 2 Inputs Gates 74LS00 Triple 3 Inputs Gates 74LS10 Dual 4 Inputs Gates 74LS20 8 Inputs Gates 74LS30 13 Inputs Gates
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