The Boundary Scan Test (BST) technology

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1 The Boundary Scan Test () technology J. M. Martins Ferreira FEUP / DEEC - Rua Dr. Roberto Frias Porto - PORTUGAL Tel / Fax: / Objectives To present in detail the boundary-scan test technology (IEEE std 49.), emphasising its application domain and access protocol J. M. Martins Ferreira - University of Porto (FEUP / DEEC) J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 2 Outline The development of BS and its application domain The BS architecture and test access port (TAP) The Scan Educator application Why Boundary Scan Test? The two main reasons that led in the mid- 8s to the development of were: The complexity of ICs made it exceedingly difficult to develop test programs for the functional test of complex PCBs Small outline surface mount devices and advanced mounting technologies almost disabled physical access to internal PCB nodes and made in-circuit test exceedingly difficult J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 3 J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 4

2 The application domain of addresses the structural test of digital printed circuit boards Keywords: structural, digital, PCBs The narrow scope of contributed to its acceptance and to the quick development of products, but the potential of a standard embedded test infrastructure goes much beyond the initial application domain J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 5 The basic concept of BS makes it possible to decouple the internal IC logic from the pins and allows direct access to any PCB node without backdriving effects Parallel input BS cell: Serial output Parallel output Serial input J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 6 The Test Access Port (TAP) The BS architecture (Test Input): The serial data input to the BS (a floating is read as a ) (Test Output): The serial data output of the BS (in high-impedance except when a scan operation is in progress) (Test Clock): Clock for the test logic (Test Mode Select): A control input that defines the operating mode required for the test logic (a floating is read as a ) Main blocks: BP Instruction TAP controller Other s /TRST TAP contr. Decoder Instruction reg. J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 7 J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 8

3 Access protocol Place the instruction in the - path Shift in a bit stream (instruction) Place the (selected) data TAP contr. in the - path Shift in (and out) the test vectors /TRST Decoder Instruction reg. The basic BS cell Three modes of operation: Transparency Controllability Observability Parallel input Serial input Serial output C/S L Parallel output Registo J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 9 J. M. Martins Ferreira - University of Porto (FEUP / DEEC) BS: The basic test protocol Shift in a new test vector (left in Shift, right in Normal or Test) Apply the test vector (left in Shift or Capture, right in Test) Capture the responses (left in Capture) Shift out the responses (left in Shift) J. M. Martins Ferreira - University of Porto (FEUP / DEEC) Is BS test slow? Scanning in and out each test vector / responses may be unacceptable for IC test, which may require hundreds of thousands of vectors However, and considering the main application domain of BS (structural testing of PCBs), we shall see that the number of test vectors required is normally small J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 2

4 BS: The test data s () The BS comprises the set of BS cells present in the circuit and is mandatory in any BS IC (at least two instructions selecting this have to be supported: EXTEST and SAMPLE / PRELOAD) The bypass is mandatory and its function is to shorten the total length of the serial PCB-level chain (it has a single bit and is selected by the BYPASS instruction) BS: The test data s (2) The identification is optional and its function is to provide a 32-bit sequence enabling the test engineer to perform an identity check on each device supporting the IDCODE instruction The user test data s are also optional and will normally interface additional testability infrastructures introduced by the designers J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 3 J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 4 The instruction : Mandatory instructions () The EXTEST instruction selects the BS and imposes the (external) test mode in each BS cell, decoupling the IC core logic from the pins (the EXTEST instruction has a pre-defined code of all-s) The SAMPLE / PRELOAD instruction also selects the BS, but the BS cells are now in transparent mode (this instruction does not have a pre-defined code) The instruction : Mandatory instructions (2) Both EXTEST and SAMPLE / PRELOAD are used to test the board interconnects, but S/P is used to shift in the first test vector BYPASS selects the -bit bypass in those ICs which do not play a role in the current test operation (the all- code is automatically loaded upon reset) J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 5 J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 6

5 The TAP controller The TAP controller is a small finite state machine that generates most of the control signals required by the BS architecture: to capture the logic value present at the parallel input of its cells to shift data serially through the cells to update the cell parallel outputs with the values that were shifted in TAP controller state Test Logic transition diagram Reset /TRST TAP contr. Decoder Instruction reg. Run Test / Idle Select DR Capture DR Shift DR Exit- DR Pause DR Exit-2 DR Update DR Select IR Capture IR Shift IR Exit- IR Pause IR Exit-2 IR Update IR J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 7 J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 8 The TAP controller () Capture, Shift and Update (-DR or -IR) are the states where the selected performs the three main test operations In the Test Logic Reset the BS is in transparent mode and the functional logic operating normally Run Test / Idle is used to perform certain test operations (such as BIST Built-In Self-Test) The TAP controller (2) Select, Exit and Exit2 (-DR or -IR) are temporary states Exit and Exit2, combined with Pause (- DR or -IR) allow shifting of test data to be temporarily halted The Select states allow selection of which type of (-DR or -IR) to place between and J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 9 J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 2

6 TAP controller timing details instructions State transitions occur with the rising edge in the signal Mandatory: EXTEST Actions in a TAP controller state occur on either the rising or the falling edge of in each state Capture takes place in the rising edge Update takes place in the falling edge SAMPLE / PRELOAD BYPASS Optional: INTEST, RUNBIST, CLAMP, IDCODE, USERCODE, HIGHZ J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 2 J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 22 Test protocol at board level TI s Scan Educator package Shift in a test vector Update the BS cell outputs (apply the test) Capture the responses Shift out the responses and (simultaneously) shift in a new test vector J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 23 J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 24

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