ECE 331 Digital System Design
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1 ECE 331 Digital System Design Introduction to and Analysis of Sequential Logic Circuits (Lecture #21) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.
2 Combinational vs. Sequential Combinational Logic Circuit Output is a function only of the present inputs. Does not have state information. Does not require memory. Sequential Logic Circuit (aka. Finite State Machine) Output is a function of the present state. Has state information Requires memory. Uses Flip-Flops to implement memory. Spring 2011 ECE Digital System Design 2
3 Synchronous vs. Asynchronous Synchronous Sequential Logic Circuit Clocked All Flip-Flops use the same clock and change state on the same triggering edge. Asynchronous Sequential Logic Circuit No clock Can change state at any instance in time. Faster but more complex than synchronous sequential circuits. Spring 2011 ECE Digital System Design 3
4 Sequential Circuits: General Model Memory Stores state information Realized using Flip-Flops Combinational Logic Implements Flip-Flop input functions and output functions Realized using logic gates, a ROM or a PLA Spring 2011 ECE Digital System Design 4
5 Sequential Circuits: Models Moore Machine Outputs are a function of the present state. Outputs are independent of the inputs. State diagram includes an output value for each state. Mealy Machine Outputs are a function of the present state and the present input. State diagram includes an input and output value for each transition (between states). Spring 2011 ECE Digital System Design 5
6 Sequential Circuits: Models Spring 2011 ECE Digital System Design 6
7 Sequential Circuits: Mealy Model output Next state Present state Spring 2011 ECE Digital System Design 7
8 Sequential Circuits: Moore Model Present state output Next state Spring 2011 ECE Digital System Design 8
9 Sequential Circuits: State Diagram Input State Output Moore Machine Each node in the graph represents a state in the sequential circuit. Spring 2011 ECE Digital System Design 9
10 Sequential Circuits: State Diagram Input Output State Mealy Machine Each node in the graph represents a state in the sequential circuit. Spring 2011 ECE Digital System Design 10
11 Sequential Circuit Analysis Spring 2011 ECE Digital System Design 11
12 Analysis: Signal Tracing 1.Assume an initial state for the sequential circuit. All Flip-Flops reset to 0 (unless otherwise stated). 2.Determine the sequential circuit output and the flipflop inputs for the first input value in the sequence. 3.Determine the next state of each Flip-Flop After the next active clock edge. 4.Determine the sequential circuit output and the flipflop inputs for the next value in the sequence. 5.Repeat steps 3 & 4. Spring 2011 ECE Digital System Design 12
13 Example: Moore Machine Flip-Flop inputs output State = AB input Spring 2011 ECE Digital System Design 13
14 Example: Moore Machine Spring 2011 ECE Digital System Design 14
15 Example: Mealy Machine Spring 2011 ECE Digital System Design 15
16 Example: Mealy Machine Spring 2011 ECE Digital System Design 16
17 Analysis: State Tables and Graphs Although constructing timing charts is satisfactory for small circuits and short input sequences, the construction of state tables and graphs provides a more systematic approach which is useful for the analysis of larger circuits and which leads to a general synthesis procedure for sequential circuits. The state table specifies the next state and output of a sequential circuit in terms of its present state and input. Spring 2011 ECE Digital System Design 17
18 Analysis Procedure 1. Determine the Flip-Flop input equations 2. Determine the Sequential Circuit output equations 3. Derive the Next State equation for each Flip-Flop Using the corresponding input equation And the Flip-Flop characteristic equation 4. Plot the Next State K-map for each Flip-Flop 5. Construct the State Table (aka. Transition Table) Assign a state label to each binary state assignment 6. Draw the corresponding state diagram (aka. state graph) Spring 2011 ECE Digital System Design 18
19 Example: Analyze a sequential circuit using D Flip-Flops Spring 2011 ECE Digital System Design 19
20 Example: Analysis (D FF) Derive the State Table for the following Sequential Logic Circuit: Spring 2011 ECE Digital System Design 20
21 Example: Analysis (D FF) The flip-flop input equations are: D A = X xor B' D B = X or A The sequential circuit output equation is: Z = A xor B The next-state equations for the flip-flops are: A + = D A = X xor B' B + = D B = X or A Spring 2011 ECE Digital System Design 21
22 Example: Analysis (D FF) The corresponding next-state (K-) maps are: Spring 2011 ECE Digital System Design 22
23 Example: Analysis (D FF) The state table, or transition table, is then: A + B + A B X = 0 X = 1 Z Present Next State State X = 0 X = 1 Output S0 S3 S1 0 S1 S0 S2 1 S2 S1 S2 0 S3 S2 S1 1 Spring 2011 ECE Digital System Design 23
24 Example: Analysis (D FF) The state diagram can then be drawn from the state table: Spring 2011 ECE Digital System Design 24
25 Example: Analyze a sequential circuit using JK Flip-Flops Spring 2011 ECE Digital System Design 25
26 Example: Analysis (JK FF) Derive the State Table for the following Sequential Logic Circuit: Spring 2011 ECE Digital System Design 26
27 Example: Analysis (JK FF) The flip-flop input equations are: J A = X.B K A = X J B = X K B = X.A The sequential circuit output equation is: Z = X.B' + X.A + X'.A'.B The next-state equations for the flip-flops are: A + = J A.A' + K A '.A A + = X.B.A' + X.A B + = J B.B' + K B '.B B + = X.B' + X.A.B Spring 2011 ECE Digital System Design 27
28 Example: Analysis (JK FF) The corresponding next-state (K-) maps are Spring 2011 ECE Digital System Design 28
29 Example: Analysis (JK FF) The state table, and transition table, is then: Spring 2011 ECE Digital System Design 29
30 Example: Analysis (JK FF) The state diagram can then be drawn from the state table: Spring 2011 ECE Digital System Design 30
31 Example: Analyze a serial adder Spring 2011 ECE Digital System Design 31
32 Example: Serial Adder The serial adder adds two n-bit binary numbers. (serial) output (serial) inputs next state present state Spring 2011 ECE Digital System Design 32
33 Example: Serial Adder Truth Table for the Full Adder: Spring 2011 ECE Digital System Design 33
34 Example: Serial Adder The state table, or transition table, is then: C i+1 Sum C i XY = 00 XY = 01 XY = 10 XY = 11 XY = 00 XY = 01 XY = 10 XY = Present Next State Output State XY = 00 XY = 01 XY = 10 XY = 11 XY = 00 XY = 01 XY = 10 XY = 11 S0 S0 S0 S0 S S1 S0 S1 S1 S Spring 2011 ECE Digital System Design 34
35 Example: Serial Adder State Graph for the Serial Adder: What type of state machine is this? Spring 2011 ECE Digital System Design 35
36 Example: Serial Adder Timing Diagram for the Serial Adder: Spring 2011 ECE Digital System Design 36
37 Example: Analyze a state machine with multiple inputs. Spring 2011 ECE Digital System Design 37
38 Example: Multiple Inputs State Table for a state machine with multiple inputs: Spring 2011 ECE Digital System Design 38
39 Example: Multiple Inputs State Graph for a state machine with multiple inputs: What type of state machine is this? How many paths leave each state? Spring 2011 ECE Digital System Design 39
40 Questions? Spring 2011 ECE Digital System Design 40
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