Register File, Finite State Machines & Hardware Control Language


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1 Register File, Finite State Machines & Hardware Control Language Avin R. Lebeck Some slides based on those developed by Gershon Kedem, and by Randy Bryant and ave O Hallaron Compsci 04 Administrivia Homework #4 is up, due Oct 20 Midterm: Median 90 May be late for office hours Thursday Morning May move Monday afternoon office hours Read Sections of text Pragmatic Logic (PF on blackboard or through Library) Today Review Logic esign Logisim demo (work through beginnergs guide) Memory: Latches, FlipFlops, Register file Finite State Machines: Sequential Circuits Hardware Control Language (if time) Compsci 04 2
2 Review: Boolean Functions, Gates and Circuits Circuits are made from a network of gates. (function compositions). Logisim demo a b a XOR(a,b) F = ~a*b + ~b*a a b XOR(a,b) b F Compsci 04 3 Review: The ALU Overflow = Zero n n2 0 ALU control ALU Slice ALU Slice ALU Slice ALU Slice a n b n a n2 b n2 a b a 0 b 0 Compsci 04 4
3 Review: Abstraction: The ALU General structure Two operand inputs Control inputs ALU Operation Input A Zero ALU Result We can build circuits for Input B Overflow Multiplication Carry Out ivision They are more complex Compsci 04 5 Review: SetReset Latch (Continued) R 0 0 R 0 0 S 0 0 S 0 Time S 0 R 0 0 Compsci 04 6
4 ata Latch ( Latch) E nable ata E Time oes not affect Output E 0 0 Compsci 04 7 FlipFlop C latch E latch E On C is transferred to the first latch and the second is stable. On C the output of the first stage is transferred to the second (output), and the first stage is stable. Key: Output changes only on the edge of a clock Logisim demos Compsci 04 8
5 Register File Register File = the set of locations for register values E.g., bit registers How do I build a Register File using FlipFlops? What other components do I need? Compsci 04 9 Register File Circuit to determine which of 32 registers? Circuit to get just the data from one of 32 registers? Compsci 04 0
6 TriState river The TriState driver is like a (one directional) switch: When the Enable is on (E=) it transfers the input to the output. When the Enable is off (E=0) it disconnects the output. E E Z E Z : High Impedance Compsci 04 Bus Connections The Bus: Many to many connections. Mutual exclusion: At most one Enable is on! Control must ensure this! Note: Bus sometimes used to denote multiple parallel wires n n2 0 E n E n2 E E 0 Compsci 04 2
7 Register Cells on a bus IE E latch OE IE E latch OE IE E latch OE IE E latch OE One can source and sink from any cell on the bus by activating the right controls, IEinput enable, and OEoutput enable. Compsci 04 3 atain 3Port Register Cell BusC BusB Complement BusA in E nable OutA OutB Stores one bit of a register Can Read onto BusA & BusB and Write from BusC Simultaneously Compsci 04 4
8 3Port Register File EC EA EB BusC BusB Bit BusA BusC BusB Bit0 BusA Compsci 04 5 Address ecode Circuit atain BusC BusB Register address: 0 E nabl e OutA BusA OutB A0 A EA B0 B EB C0 C EC Compsci 04 6
9 Register File (Four 4bit Registers) Reg3 Reg2 Reg Reg0 A3 B3 C3 A2 B2 C2 A B C A0 B0 C0 AEn AddA AddA0 B En AddB AddB 0 C En AddC AddC 0 Compsci 04 7 igital Logic Summary Given Boolean function, generate a circuit to realize the function. Constructed circuits that can add and subtract. The ALU: a circuit that can add, subtract, detect overflow, compare, and do bitwise operations (AN, OR, NOT) Shifter Memory Elements: SRLatch, Latch, FlipFlop Tristate drivers & Bus Communication vs. MUX Register Files Control Signals modify what circuit does with inputs ALU, Shift, Register Read/Write Next Finite State Machines Hardware Control Language Compsci 04 8
10 Finite State Machine S ={ s 0, s,... s n } is a finite set of states. I = { i 0, i,... i k, } is a finite set of input values. O= { o 0, o,... o m } is a finite set output values. efinition: A finite state machine is a function F:(S x I )> (S x O) that gets a sequence of input values I k I, k = 0,,2, and it produces a sequence of output values O k O, k=,2, such that: F(s k, i k ) = (s k+, o k+ ) K=0,, 2, Compsci 04 9 Finite State Machine is: Finite State Machine (Translation to English) A machine with a finite number of possible states. A machine with a finite number of possible Inputs. A machine with a finite number of possible different outputs. At each period (Clock cycle) the machine receives an input and it produces an output. The output is a function of the machine input and current state. After each period the machine changes state. The new state is a function of the input and current state. Compsci 04 20
11 Example: Traffic Light Controller N C W C C E Traffic light controller at an intersection. C S Compsci 04 2 Finite State Machine (cont.) Example: Traffic lights controller: There are four states: NG: Green light in the northsouth direction. NY: Yellow light in the northsouth direction. EG: Green light at the EastWest direction. EY: Yellow light at the EastWest direction. There are four outputs: (G;R): NorthSouth green light, EastWest red light (Y;R): NorthSouth yellow light, East West red light (R;Y): NorthSouth red light, EastWest yellow light (R;G): NorthSouth red light, EastWest green light There are four inputs: (c, c): Car at the NorthSouth, Car at EastWest (c, nc) Car at NorthSouth, Nocar at EastWest (nc, c): Nocar at NorthSouth, Car at EastWest (nc, nc): Nocar at NorthSouth, Nocar at EastWest Compsci 04 22
12 FSM Example: Traffic Light State Transitions: State Input NextState Output NG (;NC) NG (G;R) NG (;C) NY (G;R) NY  EG (Y;R) EG (NC;) EG (R;G) EG (C;) EY (R;G) EY  NG (R;Y)  means don t care Format (North/South; East/West) Compsci Finite State Machine (cont.) Finite State Machines can be represented by a graph. The graph is called a State iagram. The states are the nodes in the graph. The arcs in the graph represent state transitions. Each arc is labeled with the Inputs that cause the transition Nodes are labeled with the outputs. Compsci 04 24
13 FSM State iagram Example: Traffic light Controller I= ( ; NC) I = (;C) NG O = (G;R) NY O = (Y;R) EY O = (R;Y) EG O = (R;G) I = (C; ) I = (NC; ) Compsci State Code NG 00 NY 0 EG 0 EY Enumerate States State Coding Input Code (C;C) (C;NC) 0 (NC;C) 0 (NC;NC) 00 One bit for each Input Input is either true or false Output Code (R;G) 0000 (G;R) 0000 (Y;R) 0000 (R;Y) 0000 One bit per color for each light GYRGYR (North; East) Compsci 04 26
14 Coded State iagram (;0) I= ( ; NC) (;) I = (;C) NG 00 O = (G;R) (00;00) NY 0 (00;00) O = (Y;R) EY O = (R;Y) (00;00) EG (00;00) (;) O = (R;G) I = (C; ) 0 (0;) I = (NC; ) Compsci Example: Traffic Light Controller S = State, bits are S0 and S NS = Next State, bits are NS0 and NS IN S NS OUT NS = S0 *S *I0+S0*S *I = S *(S0 I0+S0*I) NS0 = S0 *S+S0*S *I +S0*S *I = S0 *S+S0*S OUT0 = S0 *S OUT = S0 *S OUT2 = S0*S +S0*S= S0 OUT3 = S0*S OUT4 = S0*S OUT5 = S0 *S +S0 *S= S0 Compsci 04 28
15 Traffic Controller FSM implementation Compsci General Method for FSM design etermine the problem:. raw the state diagram, 2. Write the truth table, 3. Write sumofproducts equations Compsci 04 30
16 A Simple Arrow FSM Consider those flashing arrow signs No light, one light, two lights, three lights > >> >>> Let s design the FSM to control this sign Compsci 04 3 Pattern Recognizer A pattern recognizer examines a sequence of inputs to detect when it sees the pattern 0. When it sees this pattern its output is forever. Let s design the FSM Compsci 04 32
17 Bit Equality a Bit equal b eq HCL Expression bool eq = (a&&b) (!a&&!b) Generate if a and b are equal Hardware Control Language (HCL) Very simple hardware description language Boolean operations have syntax similar to C logical operations We ll use it to describe control logic for processors Compsci Word Equality WordLevel Representation b 3 a 3 b 30 Bit equal Bit equal eq 3 eq 30 B A = Eq a 30 HCL Representation Eq bool Eq = (A == B) b a b 0 a 0 Bit equal Bit equal eq eq 0 32bit word size HCL representation Equality operation Generates Boolean value Compsci 04 34
18 BitLevel Multiplexor s Bit MUX HCL Expression b a out bool out = (s&&a) (!s&&b) Control signal s ata signals a and b Output a when s=, b when s=0 Compsci s Word Multiplexor WordLevel Representation s b 3 out 3 B A MUX Out a 3 b 30 a 30 b 0 a 0 out 30 HCL Representation int Out = [ s : A; : B; ]; Select input word A or B depending on control signal s HCL representation Case expression out Series of test : value pairs 0 Output value for first successful test Compsci 04 36
19 HCL WordLevel Examples Minimum of 3 Words C B A MIN3 Min3 int Min3 = [ A < B && A < C : A; B < A && B < C : B; : C; ]; Find minimum of three input words HCL case expression Final case guarantees match 4Way Multiplexor s s MUX4 Out4 int Out4 = [!s&&!s0: 0;!s : ;!s0 : 2; : 3; ]; n Select one of 4 inputs based on two control bits n HCL case expression n Simplify tests by assuming sequential matching Compsci RandomAccess Memory vala Read ports srca valb A Register file W valw dstw Write port srcb B Stores multiple words of memory Address input specifies which word to read or write Register file Holds values of program registers %eax, %esp, etc. Clock Register identifier serves as address I 8 implies no read or write performed Multiple Ports Can read and/or write multiple words in one cycle Each has separate address and data input/output Compsci 04 38
20 Register File Timing x 2 vala srca valb srcb A Register file B 2 x Reading Like combinational logic Output data generated based on input address After some delay Writing Like register Update only as clock rises 2 x Register file W valw dstw y 2 Rising clock 2 y Register file W valw dstw Clock Clock Compsci Summary Finite State Machines Inputs, Current State Compute Outputs and Next State HCL Language to express boolean logic Also, word level functions Homework #4 Compsci 04 40
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