# A single register, called the accumulator, stores the. operand before the operation, and stores the result. Add y # add y from memory to the acc

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1 Other architectures Example. Accumulator-based machines A single register, called the accumulator, stores the operand before the operation, and stores the result after the operation. Load x # into acc from memory Add y # add y from memory to the acc Store z # store acc to memory as z Can we have an instruction Add z, x, y # z:= x + y, (x, y, z in memory)? For some machines, YES, not in MIPS. MIPS is a load-store architecture. What is a load-store architecture?

2 Load-store architecture Only load and store instructions access the memory, all other instructions use registers as operands. What is the motivation? Primary motivation is speedup registers are faster. Reduced Instruction Set Computers (RISC) The instruction set has only a small number of frequently used instructions. This lowers processor cost, without much impact on performance. All instructions have the same length. Load-store architecture. Non-RISC machines are called CISC (Complex Instruction Set Computer). Example: Pentium

3 Another classification 3-address add r1, r2, r3 (r1 r2 + r3) 2-address add r1, r2 (r1 r1 + r2) 1-address add r1 (to the accumulator) 0-address or stack machines (see below) Example of stack architecture Push x x x x x * (y+z) Push y y y+z Push z z Add Multiply Pop z Computes z = x * (y + z)

4 Computer Arithmetic How to represent negative integers? The most widely used convention is 2 s complement representation. +14 = 0, = 1, Largest integer represented using n-bits is + 2 n-1-1 Smallest integer represented using n-bits is - 2 n-1 Review binary-to decimal and binary-to-hex conversions. Review BCD (Binary Coded Decimal) and ASCII codes. How to represent fractions?

5 Overflow +12 = 0, = 0, = 0, = 0, add add +14 = 0, ? = 1, Addition of a positive and a negative number does not lead to overflow. How to detect overflow? Some machines use the following instructions: Add the operands B (overflow) OVERFLOW #sets condition codes # conditional branch Z N V C Condition code register Not MIPS

6 Exceptions MIPS instructions that detect overflow cause an exception (also called an interrupt), and transfer control to a predefined address to invoke a routine for handling the exception. L: add \$t0, \$t1, \$t2 overflow! Return address (L+4) is saved in EPC Next instruction Exception handler routine Ra EPC jr ra Exceptions cause unscheduled procedure calls.

7 The following sequence of MIPS instructions can detect overflow in signed addition: addu \$t0, \$t1, \$t2 xor \$t3, \$t1, \$t2 # add but don t trap # check if signs differ slt \$t3, \$t3, \$zero # \$t3=1 if signs differ bne \$t3 \$zero, no_overflow xor \$t3, \$t0, \$t1 # sum sign = operand sign? slt \$t3, \$t3, \$zero # if not, then \$t3=1 bne \$t3, \$zero, overflow no_overflow: overflow:

8 More Programming Examples Copying a string a0 Each char is represented array x by an ASCII byte. In C, s0. a string is terminated by a 0 (Null in ASCII). s0 will hold the array index. a1 array y I O W A null add \$s0, \$zero, \$zero # i = 0 L1: add \$t1, \$a1, \$s0 # address of y[i] in t1 lb \$t2, 0(\$t1) add \$t3, \$a0, \$s0 sb \$t2, 0(\$t3) # t2 = y[i] # address of x[i] in t3 # x[i] = y[i] addi \$s0, \$s0, 1 # i = i+1 bne \$t2,\$zero, L1 # if y[i] 0 then goto L1

9 Loading a 32-bit constant into a register lui \$t0,255 (load upper-byte immediate) \$t addi \$t0, \$t0, 15, (add immediate), or ori \$t0, \$t0, 15 (or immediate) \$t This is how the la (pseudo-instruction) is implemented.

10 Example of shift instructions sll \$t2, \$s0, 8 # \$t2 = \$s0 << 8 bits (shift left logical) What is it used for? (shift right logical) What is it used for? Multiplication (or division) by 2 k Character manipulation etc.

11 Logic Design (Go to Appendix B) When you write add \$t0, \$t1, \$t2, you imagine something like this: \$t1 Adder \$t0 \$t2 What kind of hardware can ADD two binary integers? We need to understand about GATES and BOOLEAN ALGEBRA, that are foundations of logic design.

12 AND gate X Y X.Y X X.Y Y OR gate X Y X+Y X X+Y Y NOT gate X X 0 1 X X 1 0 Typically, logical 1 = +3.5 volt, and logical 0 = 0 volt. Other representations are possible.

13 Analysis of logical circuits X F Y What is the value of F when X=0 and Y=1? Draw a truth table. X Y F This is the exclusive or (XOR) function. In algebraic form F= X.Y + X.Y

14 More practice 1. Let A.B + A.C = 0. What are the values of A, B, C? 2. Let (A + B + C). (A + B + C) = 0. What are the possible values of A, B, C? Draw truth tables. Draw the logic circuits for the above two functions. A B C

15 Elementary Boolean Algebra A + A = 1 A. A = A = 1 1. A = A 0. A = A = A A + A = A A. A = A A. (B + C) = A.B + A.C Distributive Law A + B.C = (A+B). (A+C) A. B = A + B De Morgan s theorem A + B = A. B

16 Synthesis of logic circuits Many problems of logic design can be specified using a truth table. Give such a table, can you design the logic circuit? Design a logic circuit with three inputs A, B, C and one output F such that F=1 only when a majority of the inputs is equal to 1. A B C F Sum of product form F = A.B.C + A.B.C + A.B.C + A.B.C Draw a logic circuit to generate F

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