Binary full adder. 2-bit ripple-carry adder. CSE 370 Spring 2006 Introduction to Digital Design Lecture 12: Adders

Transcription

1 SE 370 Spring 2006 Introduction to Digital Design Lecture 12: dders Last Lecture Ls and Ls Today dders inary full 1-bit full omputes sum, carry-out arry-in allows cascaded s = xor xor = ND2 11 ND2 12 ND OR3 S Full dder Full : lternative Implementation Multilevel logic Slower Less gates 2 s, 2 NDs, 1 OR = ( ) = + + = ( ) + Half dder xor S Half dder xor xor ( xor ) bit ripple-carry ND2 11 ND2 12 ND2 33 OR3 1 1-it dder Overflow

2 -bit ripple-carry /subtractor Overflow ircuit adds or subtracts 2s complement: = + ( ) = + ' ' Sel ' 1 11' 0 00' 0 1 Sel 0 1 Sel 0 1 Sel S3 S2 S1 S0 Note: an replace 2:1 muxes with gates 0 dd 1 Subtract roblem: Ripple-carry delay arry propagation limits speed N N N 32 ND2 11 ND2 12 ND OR3 N+1 N takes two gate delays arrives late 2 2 S S1 S3 Ripple-carry timing diagram ritical delay arry propagation = is worst case S0, 1 Valid S1, 2 Valid S2, 3 Valid S3, Valid T0 T2 T T6 T8 One solution: arry lookahead logic ompute all the carries in parallel Derive carries from the data inputs Not from intermediate carries Use two-level logic ompute all sums in parallel ascade simple s to make large s Speed improvement 16-bit ripple-carry: ~32 gate delays 16-bit carry-lookahead: ~8 gate delays Issues omplex combinational logic S0

3 Full again arry-lookahead logic i i i i i Half dder xor i 36 ND2 i 37 Half dder xor xor ( xor ) 38 ND2 39 OR2 0 Si i+1 arry generate: i = i i enerate carry when = = 1 arry propagate: i = i xor i ropagate carry-in to carry-out when ( xor ) = 1 and in terms of generate/propagate: S i = i xor i xor i = i xor i i+1 = i i + i ( i xor i ) = i + i i arry-lookahead logic (cont d) Re-express the carry logic in terms of and 1 = = = = = = = Implement each carry equation with two-level logic Derive intermediate results directly from inputs Rather than from carries llows "sum" computations to proceed in parallel i i i 1 Implementing the carrylookahead logic gate delay 2 gate delays 1 gate delay Logic complexity increases with size 1 2 3

4 [15-12] [15-12] 12 -bit dder ascaded carry-lookahead four-bit s with internal carry lookahead Second level lookahead extends to 16 bits [11-8] -bit dder [11-8] 8 [7-] -bit dder [7-] [3-0] -bit dder [3-0] nother solution: arry-select Redundant hardware speeds carry calculation ompute two high-order sums while waiting for carryin () Select correct high-order sum after receiving 8 -bit [7:] 0 low S[11-8] S[7-] bit [7:] 1 high Lookahead arry Unit -0 five 2:1 muxes -it dder [3:0] 8 S7 S6 S5 S S3 S2 S1 S0 We've finished combinational logic... What you should know Twos complement arithmetic Truth tables asic logic gates Schematic diagrams Timing diagrams Minterm and maxterm expansions (canonical, minimized) de Morgan's theorem ND/OR to NND/NOR logic conversion K-maps, logic minimization, don't cares Multiplexers/demultiplexers Ls/Ls ROMs dders Sequential versus combinational pply fixed inputs, Wait for edge Observe Wait for another edge Observe again ombinational: will stay the same Sequential: may be different

5 Sequential logic Two types Synchronous = ed synchronous = self-timed Has state State = memory Employs feedback ssumes steady-state signals Signals are valid after they have settled State elements hold their settled output values Sequential versus combinational (again) ombinational systems are memoryless Outputs depend only on the present inputs Inputs System Outputs Sequential systems have memory Outputs depend on the present and the previous inputs Inputs System Outputs Feedback Synchronous sequential systems Memory holds a system s state hanges in state occur at specific times periodic signal times or s the state changes The period is the time between state changes Steady-state abstraction Outputs retain their settled values The period must be long enough for all voltages to settle to a steady state before the next state change pulsewidth State changes occur at rising edge of duty cycle = pulsewidth/period (here it is 50%) lock hides transient behavior period Settled value

6 Example: sequential system Door combination lock Enter 3 numbers in sequence and the door opens If there is an error the lock must be reset fter the door opens the lock must be reset Inputs: Sequence of numbers, reset Outputs: Door open/close Memory: Must remember the combination