Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case )

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1 l Advanced Process Technology l Surface Mount (IRF9Z34S) l Low-profile through-hole (IRF9Z34L) l 175 C Operating Temperature l Fast Switching l P- Channel l Fully Avalanche Rated Description Third Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The D 2 Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The D 2 Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRF9Z34L) is available for lowprofile applications. G PD A IRF9Z34S/L HEXFET Power MOSFET D S 2 D Pak TO-262 V DSS = -60V R DS(on) = 0.14Ω I D = -18A Absolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V 10V -18 I T C = 100 C Continuous Drain Current, V 10V -13 A I DM Pulsed Drain Current -72 P A = 25 C Power Dissipation 3.7 W P C = 25 C Power Dissipation 88 W Linear Derating Factor 0.59 W/ C V GS Gate-to-Source Voltage ± 20 V E AS Single Pulse Avalanche Energy 370 mj I AR Avalanche Current -18 A E AR Repetitive Avalanche Energy 8.8 mj dv/dt Peak Diode Recovery dv/dt ƒ -4.5 V/ns T J Operating Junction and -55 to T STG Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case ) C Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 1.7 C/W R θja Junction-to-Ambient ( PCB Mounted,steady-state)** 40 8/25/97

2 Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage -60 V V GS = 0V, I D = -250µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I D =-1mA R DS(on) Static Drain-to-Source On-Resistance 0.14 Ω V GS =-10V, I D = -11A V GS(th) Gate Threshold Voltage V V DS = V GS, I D = -250µA g fs Forward Transconductance 5.9 S V DS = -25V, I D = -11A I DSS Drain-to-Source Leakage Current -100 V µa DS = -60V, V GS = 0V -500 V DS = -48V, V GS = 0V, T J = 150 C I GSS Gate-to-Source Forward Leakage -100 V GS = -20V na Gate-to-Source Reverse Leakage 100 V GS = 20V Q g Total Gate Charge 34 I D = -18A Q gs Gate-to-Source Charge 9.9 nc V DS = -48V Q gd Gate-to-Drain ("Miller") Charge 16 V GS = -10V, See Fig. 6 and 13 t d(on) Turn-On Delay Time 18 V DD = -30V t r Rise Time 120 I D = -18A ns t d(off) Turn-Off Delay Time 20 R G = 12Ω t f Fall Time 58 R D = 1.5Ω, See Fig. 10 L S Internal Source Inductance 7.5 nh Between lead, and center of die contact C iss Input Capacitance 1100 V GS = 0V C oss Output Capacitance 620 pf V DS = -25V C rss Reverse Transfer Capacitance 100 ƒ = 1.0MHz, See Fig. 5 Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol (Body Diode) -18 showing the A I SM Pulsed Source Current integral reverse G (Body Diode) -72 p-n junction diode. S V SD Diode Forward Voltage -6.3 V T J = 25 C, I S = -18A, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = -18A Q rr Reverse Recovery Charge nc di/dt = 100A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S +L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 ) V DD = -25V, starting T J = 25 C, L = 1.3mH R G = 25Ω, I AS = -18A. (See Figure 12) ƒ I SD -18A, di/dt 170A/µs, V DD V (BR)DSS, T J 175 C Pulse width 300µs; duty cycle 2%. Uses IRF9Z34 data and test conditions ** When mounted on 1" square PCB (FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994.

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7 Peak Diode Recovery dv/dt Test Circuit IRF9Z34S/L D.U.T* + ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer V GS R G dv/dt controlled by R G I SD controlled by Duty Factor "D" D.U.T. - Device Under Test + - V DD * Reverse Polarity of D.U.T for P-Channel Driver Gate Drive Period P.W. D = P.W. Period [ V GS =10V] *** D.U.T. I SD Waveform Reverse Recovery Current Re-Applied Voltage Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt Inductor Curent Body Diode Ripple 5% Forward Drop [ V DD ] [ ] I SD *** V GS = 5.0V for Logic Level and 3V Drive Devices Fig 14. For P-Channel HEXFETS

8 D 2 Pak Package Outline 1.40 (.055) MAX (.415) (.405) - A (.185) 4.20 (.165) - B (.052) 1.22 (.048) (.400) RE F (.255) 6.18 (.243) 1.78 (.070) 1.27 (.050) (.610) (.580) 2.79 (.110) 2.29 (.090) 5.28 (.208) 4.78 (.188) 2.61 (.103) 2.32 (.091) 3X 1.40 (.055) 1.14 (.045) 5.08 (.200) 3X 0.93 (.037) 0.69 (.027) 0.55 (.022) 0.46 (.018) 1.39 (.055) 1.14 (.045) 8.89 (.350) RE F (.010) M B A M MINIMUM RECOMMENDED FOOTPRINT (.450) NOTES: 1 DIMENSIONS AFTER SOLDER DIP. 2 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION : INCH. 4 HEATSINK & LEAD DIMENSIONS DO NOT INCLUDE BURRS. LEAD ASSIGNMENTS 1 - G ATE 2 - DRA IN 3 - S OU RC E 8.89 (.350) 3.81 (.150) (.700) 2.08 (.082) 2X 2.54 (.100) 2X Part Marking Information D 2 Pak IN TER NATION AL RECTIFIER LOGO ASSEMBLY LOT CODE F530S B 1M A PART NUMBER DATE CODE (YYWW ) YY = YEAR WW = WEEK

9 Package Outline TO-262 Outline Part Marking Information TO-262

10 Tape & Reel Information D 2 Pak TRR 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) (.0145) (.0135) FEED DIRECTION TRL 1.85 (.073) 1.65 (.065) (.429) (.421) (.457) (.449) (.634) (.626) 1.75 (.069) 1.25 (.049) (.609) (.601) (.957) (.941) 4.72 (.136) 4.52 (.178) FEED DIRECTION (.532) (.504) (1.079) (.941) (14.173) M AX (2.362) MIN. NOTES : 1. CO MFOR MS TO EIA CO NTRO LLING DIMENSION: MILLIMETER. 3. DIMENSIO N HUB. 4. INCLUDES FLANGE OUTER EDGE (1.039) (.961) (1.197) MA X. 4 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) IR GERMANY: Saalburgstrasse 157, Bad Homburg Tel: IR ITALY: Via Liguria 49, Borgaro, Torino Tel: IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: Data and specifications subject to change without notice. 8/97