Absolute Maximum Ratings Parameter Max. Units

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1 l l l l l Advanced Process Technology Surface Mount (IRFZ46S) Low-profile through-hole (IRFZ46L) 175 C Operating Temperature Fast Switching Description Third Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The D 2 Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The D 2 Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRFZ46L) is available for lowprofile applications. G PD A IRFZ46S/L HEXFET Power MOSFET D S 2 D Pak TO-262 V DSS = 50V R DS(on) = 0.024Ω I D = 72A Absolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V 10V 50 I T C = 100 C Continuous Drain Current, V 10V 38 A I DM Pulsed Drain Current 220 P A = 25 C Power Dissipation 3.7 W P C = 25 C Power Dissipation 150 W Linear Derating Factor 1.0 W/ C V GS Gate-to-Source Voltage ± 20 V E AS Single Pulse Avalanche Energy 100 mj dv/dt Peak Diode Recovery dv/dt ƒ 4.5 V/ns T J Operating Junction and -55 to C T STG Storage Temperature Range C Soldering Temperature, for 10 seconds 300 (1.6mm from case ) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 1.0 C/W R θja Junction-to-Ambient ( PCB Mounted,steady-state)** 40 8/25/97

2 Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 50 V V GS = 0V, I D = 250µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I D =1mA R DS(on) Static Drain-to-Source On-Resistance Ω V GS =10V, I D = 32A V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µA g fs Forward Transconductance 27 S V DS = 25V, I D = 32A I DSS Drain-to-Source Leakage Current 25 V DS = 50V, V GS = 0V µa 250 V DS = 48V, V GS = 0V, T J = 150 C I GSS Gate-to-Source Forward Leakage 100 V GS = 20V na Gate-to-Source Reverse Leakage -100 V GS = -20V Q g Total Gate Charge 66 I D = 54A Q gs Gate-to-Source Charge 21 nc V DS = 48V Q gd Gate-to-Drain ("Miller") Charge 25 V GS = 10V, See Fig. 6 and 13 t d(on) Turn-On Delay Time 12 V DD = 28V t r Rise Time 120 I D = 54A ns t d(off) Turn-Off Delay Time 42 R G = 9.1Ω t f Fall Time 96 R D = 0.49Ω, See Fig. 10 L S Internal Source Inductance 7.5 nh Between lead, and center of die contact C iss Input Capacitance 1800 V GS = 0V C oss Output Capacitance 960 pf V DS = 25V C rss Reverse Transfer Capacitance 160 ƒ = 1.0MHz, See Fig. 5 Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol (Body Diode) 50 showing the A I SM Pulsed Source Current integral reverse G 220 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage 2.5 V T J = 25 C, I S = 54A, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 54A Q rr Reverse Recovery Charge nc di/dt = 100A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S +L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 ) V DD = 25V, starting T J = 25 C, L = 34µH R G = 25Ω, I AS = 54A. (See Figure 12) ƒ I SD 54A, di/dt 250A/µs, V DD V (BR)DSS, T J 175 C Pulse width 300µs; duty cycle 2%. Uses IRFZ46 data and test conditions Calculated continuous current based on maximum allowable junction temperature; for recommended current-handling of the package refer to Design Tip # 93-4 ** When mounted on 1" square PCB (FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994.

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7 Peak Diode Recovery dv/dt Test Circuit D.U.T + ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test + - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =10V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS

8 D 2 Pak Package Outline 1.40 (.055) MAX (.415) (.405) - A (.185) 4.20 (.165) - B (.052) 1.22 (.048) (.400) RE F (.255) 6.18 (.243) 1.78 (.070) 1.27 (.050) (.610) (.580) 2.79 (.110) 2.29 (.090) 5.28 (.208) 4.78 (.188) 2.61 (.103) 2.32 (.091) 3X 1.40 (.055) 1.14 (.045) 5.08 (.200) 3X 0.93 (.037) 0.69 (.027) 0.55 (.022) 0.46 (.018) 1.39 (.055) 1.14 (.045) 8.89 (.350) RE F (.010) M B A M MINIMUM RECOMMENDED FOOTPRINT (.450) NOTES: 1 DIMENSIONS AFTER SOLDER DIP. 2 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION : INCH. 4 HEATSINK & LEAD DIMENSIONS DO NOT INCLUDE BURRS. LEAD ASSIGNMENTS 1 - G ATE 2 - DRA IN 3 - S OU RC E 8.89 (.350) 3.81 (.150) (.700) 2.08 (.082) 2X 2.54 (.100) 2X Part Marking Information D 2 Pak IN TER NATION AL RECTIFIER LOGO ASSEMBLY LOT CODE F530S B 1M A PART NUMBER DATE CODE (YYWW ) YY = YEAR WW = WEEK

9 Package Outline TO-262 Outline Part Marking Information TO-262

10 Tape & Reel Information D 2 Pak TRR 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) (.0145) (.0135) FEED DIRECTION TRL 1.85 (.073) 1.65 (.065) (.429) (.421) (.457) (.449) (.634) (.626) 1.75 (.069) 1.25 (.049) (.609) (.601) (.957) (.941) 4.72 (.136) 4.52 (.178) FEED DIRECTION (.532) (.504) (1.079) (.941) (14.173) M AX (2.362) MIN. NOTES : 1. CO MFOR MS TO EIA CO NTRO LLING DIMENSION: MILLIMETER. 3. DIMENSIO N HUB. 4. INCLUDES FLANGE OUTER EDGE (1.039) (.961) (1.197) MA X. 4 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) IR GERMANY: Saalburgstrasse 157, Bad Homburg Tel: IR ITALY: Via Liguria 49, Borgaro, Torino Tel: IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: Data and specifications subject to change without notice. 8/97

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