# Logic Reference Guide

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1 Logic eference Guide Advanced Micro evices INTOUCTION Throughout this data book and design guide we have assumed that you have a good working knowledge of logic. Unfortunately, there always comes a time when you are called on to remember something which can only be found in that logic textbook which you threw away years ago. This section is intended to provide a quick review and reference of the basic principles of digital logic. We will cover three general areas: Basic logic elements Basic storage elements Binary numbers Throughout the text, we will use the notation that was used throughout this book. If you are unfamiliar with the syntax, you will probably find it easy to understand as you read; if you wish for a more detailed explanation of the symbols, please refer to the Basic esign with PLs section where they are defined. As this is a logic reference only, we cannot take on lengthy discussions, nor can we train you in the basic principles of digital logic if you have not previously been trained. In such a case, we must refer you to your favorite logic textbook. BAIC LOGIC ELEMENT In this section, we will discuss the concepts surrounding combinatorial logic functions. The Three Basic Gates There are three basic logic gates from which all other combinatorial logic functions can be generated. These functions are NOT, AN, and O. A truth table indicating these functions is shown in Table 1. ince they can be used to generate any function, they are said to be functionally complete. Table 1. Truth Table for the NOT, AN, and O Functions A B /A A*B A+B The standard schematic symbols used to represent these gates are shown in Figure 1. NOT AN O 9A-1 Figure 1. chematics ymbols for the Three Fundamental Gates The AN and NOT functions can be combined into the NAN function. This is equivalent to an AN gate followed by an inverter, as shown in Figure 2a. Likewise, the O and NOT gates can be combined into the NO function, as shown in Figure 2b. Each of these gates is functionally complete; any logic function can be expressed solely as a function of NAN or NO gates. = a. The NAN Function = b. The NO Function Figure 2. The NAN and NO Functions Precedence of Operators 9A-2 Logic functions may be created with any combination of the three basic functions. How those functions are expressed affects the evaluation of the function. The normal order of evaluation is: NOT, AN, O Evaluation proceeds in order from left to right. Publication# 9 ev. A Amendment /0 Issue ate: une

2 This order may be altered by inserting parentheses in the function. The contents of the parentheses will always be evaluated before the rest of the expression, from left to right. ome example functions are evaluated in Table 2. Table 2. Using Parentheses to Change the Order of Evaluation A*B+/A* A*B+/A* A*(B+/A)* A*(B+/A)* A B C C+ (C+) C+ (C+) Commutative, Associative, and istributive Laws The AN and O functions are commutative and associative. This means that the operands can appear in any order without affecting the evaluation of the function. This is illustrated in Tables 3 and 4. Table 3. Commutativity A B A*B B*A A+B B+A Table 4. Associativity A B C (A*B)*C A*(B*C) (A+B)+C A+(B+C) uality The two distributive laws give an example of the concept of duality. This principle states that: Any identity will also be true if the following substitutions are made: * for + + for * 1 for 0 0 for 1 Thus, it is only necessary to prove the first of the distributive laws; the second one will then be true by duality. Note that duality is not required to prove the second law; it can also be proven by truth table or by logic manipulation. Manipulating Logic Logic functions may be manipulated by the use of Boolean algebra. The logic functions may be expressed in one of the two canonical forms, or by using a simplified expression. There are actually two distributive laws; one of them resembles standard algebra more than the other. These two laws state that: A*(B+C) = (A*B) + (A*C) A+(B*C) = (A+B) * (A+C) 6-4 Logic eference Guide

3 Canonical Forms There are two fundamental canonical forms: sum-ofminterms and product-of-maxterms. The former is by far the most widespread. These are special cases of what are more generally referred to as sum-of-products and product-of-sums forms. Minterms and maxterms are products and sums of the variables involved in a function. Each particular combination of noninverted and inverted variables in a product or sum is given a minterm or maxterm number, as shown in Table 5. Within each minterm or maxterm, the individual variables are referred to as literals. For the case of sum-of-minterms form, the expression for a function may be found by Oing the minterms which correspond to the 1 s in the function s truth table. Likewise, the product-of-maxterms expression may be found by ANing the maxterms which correspond to the 0 s in the truth table. This is illustrated in Figure 3. Table 5. Minterms and Maxterms Table of Minterms for Three Variables Table of Maxterms for Three Variables Minterm /x*/y*/z /x*/y*z /x*y*/z /x*y*z x*/y*/z x*/y*z x*y*/z x*y*z Name m0 m1 m2 m3 m4 m5 m6 m7 Maxterm Name x + y + z M0 x + y +/z M1 x +/y + z M2 x +/y + /z M3 /x + y + z M4 /x + y + /z M5 /x + /y + z M6 /x + /y + /z M7 Conversion Between Canonical Forms It is a simple matter to convert between canonical forms. Given a truth table for a function F, there are four different representations that can be used: One can convert back and forth between these representations by using the rules shown in Table 6. um-of-minterms form of F Product-of-maxterms form of F um-of-minterms form of /F Product-of-maxterms form of /F Logic eference Guide 6-5

4 Minterm/ Maxterm A B C X Y Number a. Truth Table X = m0+m2+m3+m5+m7+m8+m9 = m (0,2,3,5,7,8,9) = /A * /B * /C * / ;m0 + /A * /B * C * / ;m2 + /A */B* C * ;m3 + /A * B * /C * ;m5 + /A * B * C * ;m7 + A * /B * /C * / ;m8 + A */B* /C * ;m9 Y = m0+m1+m2+m3+m4+m7+m8+m9 = m (0,1,2,3,4,7,8,9) = /A * /B * /C * / ;m0 + /A */B* /C * ;m1 + /A */B* C * /;m2 + /A */B* C * ;m3 + /A * B * /C * / ;m4 + /A * B * C * ;m7 + A */B* /C * /;m8 + A */B* /C * ;m9 X = M1*M4*M6*M*M*M12*M13*M14*M15 ΠM (1,4,6,,,12,13,14,15) =(A+B+C+/) ;M1 *(A+/B+C+) ;M4 *(A+/B+/C+) ;M6 *(/A+B+/C+) ;M *(/A+B+/C+/) ;M *(/A+/B+C+) ;M12 *(/A+/B+C+/) ;M13 *(/A+/B+/C+) ;M14 *(/A+/B+/C+/) ;M15 Y = M5*M6*M*M*M12*M13*M14*M15 = ΠM (5,6,,,12,13,14,15) =(A+/B+C+/) ;M5 *(A+/B+/C+) ;M6 *(/A+B+/C+) ;M *(/A+B+/C+/) ;M *(/A+/B+C+) ;M12 *(/A+/B+C+/) ;M13 *(/A+/B+/C+) ;M14 *(/A+/B+/C+/) ;M15 b. The um-of-minterms Expression c. The Product-of-Maxterms Expression Figure 3. Finding the Canonical Form from the Truth Table 6-6 Logic eference Guide

5 Table 6. Conversion of Forms Table AM esired Form Given Form Minterm Maxterm Inverted Minterm Inverted Maxterm Expansion of F Expansion of F Expansion of F Expansion of F Minterm Maxterm numbers List Minterms not Maxterm numbers expansion are those numbers present in F are the same as of F not in the Minterm Minterm numbers list of F of F Maxterm Minterm numbers Minterm numbers expansion are those numbers are the same as List Maxterms not of F not on the Maxterm Maxterm numbers present in F list of F of F implifying Logic Canonical forms are convenient in that it is easy to derive and convert them. However, the representation is bulky, since all variables must appear in each sum or product. These expressions can be simplified by applying the basic laws and theorems of Boolean algebra. Table 7. Postulates and Theorems of Boolean Algebra There are four basic postulates, two of which are the commutative and distributive laws which were discussed above. From these postulates, it is possible to derive nine basic theorems. The postulates and theorems are listed in Table 7. Postulate 1 (A) X + FALE = X (B) X*TUE = X Postulate 2 (A) X + /X = TUE (B) X * /X = FALE Postulate 3 (A) X + Y = Y + X (B) X*Y = Y*X Postulate 4 (A) X * (Y + Z) = (X*Y) + (X*Z) (B) X + (Y*Z) = (X + Y) * (X + X) Theorem 1 (A) X + X = X (B) X * X = X Theorem 2 (A) X + TUE = FALE (B) X*FALE = FALE Theorem 3 / (/X) = X Theorem 4 (A) X + (Y + Z) = (X + Y) + Z (B) X * (Y*Z) = (X*Y) * Z Theorem 5 (A) / (X + Y) = /X * /Y (B) / (X * Y) = /X + /Y Theorem 6 (A) X + (X * Y) = X (B) X * (X + Y) = X Theorem 7 (A) (X*Y) + (X*/Y) = X (B) (X + Y) * (X + /Y) = X Theorem 8 (A) X + (/X*Y) = X + Y (B) X * (/X + Y) X*Y Theorem 9 (A) (X*Y) + (/X*Z) + (Y*Z) = (X*Y) + (/X*Z) (B) (X + Y) * (/X + Z) * (Y + Z) = (X + Y)*(/X + Z) Notice that each theorem and postulate (with the exception of theorem 3) has two forms. This is a result of the duality principle; once one form of a theorem is established, the dual representation follows immediately. Theorem 3 has no dual because it does not involve any of the elements that have duals (+, *, 1, or 0). As the logic expression is simplified, it no longer contains minterms (or maxterms), since some of the minterms and literals are being eliminated. What was a sum-of-minterms (product of maxterms) representation is now simplified to a sum-of-products (product of sums). Logic eference Guide 6-7

6 emorgan s Theorem Once an expression has been simplified, it is no longer possible to invert the function by using Table 6. Inverting simplified logic requires emorgan s theorem: /(X*Y) = /X + /Y /(X + Y) = /X*/Y This is theorem 5 in Table 7. There is one shortcut which can be used. The effect of inversion can be accomplished by inverting all literals and then using the dual representation. For example, given the expression /(A*/B + A*C + /A*B*) A C B 0 1 Values of C Values of A Values of B Moving to an Adjacent Cell Changes the Value of one Variable only. Groups Can Wrap Around 9A-3 we can invert to obtain: /A*B + /A*/C + A*/B*/ ;step one, invert literals (/A + B)*(/A + /C)* ;step two, (A + /B + /) take dual This expression must still be simplified to obtain a sumof-products representation, but this shortcut eliminates some of the early steps. arnaugh Maps: Minimizing Logic implifying by hand by using algebraic manipulation can be a tedious and error-prone procedure. When only a few variables are used (generally less than 5 or 6), arnaugh maps (also called -maps) provide a simpler graphical means of simplifying logic. -maps not only allow for logic simplification, but for logic minimization, where an expression has a minimal number of product terms (or sum terms) and literals. A arnaugh map consists of a box which has one cell for each minterm. These cells are arranged so that only one literal is inverted when moving from one cell to an adjacent cell. The headings placed by each row and column indicate the polarities of the literals for that row or column. The literals themselves are indicated in the top left corner of the map. An example of a arnaugh map for three variables is shown in Figure 4. Figure 4. A arnaugh Map for Three Variables The truth table for a function is then transferred to the -map by placing the 1 s and 0 s in the appropriate cells. ince each cell differs from its neighbor only in the polarity of one of the literals, 1 s in adjacent cells can be combined by theorem 7a, which says that x*y + x*/y = x In this manner, two product terms are combined into one. This procedure can conceptually be repeated to allow groupings of two, four, eight, or any group of adjacent cells whose size is a power of two. A cell may appear in more than one group. ust enough groups are found to include all of the 1 s. The groups should be as large as possible. This process provides a minimal sum of products. The product-of-sums form can be obtained by grouping 0 s instead of 1 s and inverting the header for each cell. The two functions from Figure 3 have been placed into -maps in Figure 5. The groups are then used as individual product terms. When reading the product terms from the map, the only literals which will appear in the product term are the ones whose values are constant for each cell in the group. If that value is 1, then the noninverted form of the literal is used. If the value is 0, then the inverted form of the literal is used. For active-low functions, the same procedure is used, except that the 0 s are grouped instead of the 1 s. The active-low version of the functions from Figure 3 are derived in Figure 6. Hand simplification and minimization is not needed as frequently today as in the past, since software is now available for handling these logic manipulations. Most software can perform logic simplification and minimization automatically. 6-8 Logic eference Guide

7 C A B A*/C*/ C A B /C*/ 1 1 B*/C* A*B*/C 1 0 /A*/B*/C /A*/B*/ X /A*/C*/ /A*/ Y X = /A*/B*/ + A*/C*/ + B*/C* + /A*C*/ Y = /A*/ + /C*/ + /A*/B*/C + A*B*/C 9A-4 Figure 5. Using a -map to Minimize the Functions in Figure 3 C A B A*B*/C*/ C A B /A*B* /B* A*/B* C* C* A*C X A*C Y /X = C* + /B* + A*C + /A*B*/C*/ /Y = C* + A* + /A*B* + A*/B* 9A-5 Figure 6. Finding Inverse Functions Logic eference Guide 6-9

8 Comparison and Equivalence: the XO and XNO Gates The Exclusive-O (XO) and Exclusive-NO (XNO) gates are two special gates which are relatively common. These gates have schematic symbols as shown in Figure 7a. They are actually compound gates, and can be generated by AN, O, and NOT gates using the functions: x :+: y = x*/y + /x*y ;XO gate x :*: y = x*y + /x*/y ;XNO gate The XO and XNO functions are actually inverses of each other; that is, x :+: y = /(x :*: y) The truth tables for these gates are shown in Figure 7b. Note that the XO function is true if and only if the operands are different. For this reason, it is useful as a comparator. The XNO function is true if and only if its operands are the same; therefore it is used as an equivalence indicator. XO XNO a. chematic ymbols 9A-6 A B A:+:B A:*:B b. XO and XNO Truth Table Figure 7. The Exclusive-O and Exclusive-NO Functions ome basic properties of the XO and XNO functions are listed in Table 8. Table 8. Properties of the XO and XNO Functions XO XNO x :+: 0 = x x :*: 0 = /x x :+ 1 = /x x :*: 1 = x x :+: x = 0 x :*: x = 0 x :+: /x = 1 x :*: /x = 1 x :+: y = y :+: x x :*: y = y :*: x x :+: y = :+: z = (x :+: y) :+: z x :*: y :*: z = (x :*: y) :*: z) = x :+: (y :+: z) = x :*: (y :*: z) x :+: y = /x :+: /y x :*: y = /x :*: /y / (x :+: y) = /x :+: y / (x :*: y) = /x :*: y = x :+: /y = x :*: /y = x :+: y = x :+: y x :+: y = x* /y + /x*y x :*: y = x* y + /x*/y x :+: x* y = x*/y x :*: x* y = /x + y x :+: /x*y = x + y x :*: /x*y = /x * /y x* (y :+: z) = (x*y) :+: (x*z) x + (y :*: z) = (x + y) :*: (x + z) /x*(y :+: z) = (x + y) :+: (x + z) /x + (y :*: z) = (x*y) :*: (x*z) When deriving equations from a arnaugh map, XO and XNO functions can usually be identified by their characteristic pattern. Exactly what the operands are may or may not be obvious for more complicated functions. ome examples are shown in Figure 8. The XO gate can be used as an UNLE operator. In other words, the function, A = X :+: Y can be interpreted as: A will have the same value as X UNLE Y is true. This can be helpful when trying to derive a logic equation for a function which can be described in words. 6- Logic eference Guide

9 P P = /P*/*/ + P**/ + /P** + P*/* = ((/P*/) + (P*))*/ + ((/P*)+(P*/))* = (P:*:)*/ + (P:+:)* = /(P:+:)*/ + (P:+:)* = /P*/* + P** + P*/*/ = ((/P*/) + (P*))* + P*/*/ = (P:*:)* + P*//*/ = (P:+:):*: 9A-7 Figure 8. Finding XO and XNO Functions in arnaugh Maps Basic torage Elements torage elements provide circuits with the capability of remembering past conditions or events. The prototypical storage element is just a pair of cross-coupled NAN gates, as shown in Figure 9. These elements are normally called flip-flops. Flip-flops can also be characterized by their control scheme. There are four types of flip-flops, each of which can be unclocked or clocked: - - T The discussion below will be divided between unclocked and clocked flip-flops. Each of the four flip-flop types will be treated for each section. Figure 9. Basic torage Element 9A-8 In general, there are two primary classes of flip-flops: Unclocked flip-flops, or latches Clocked flip-flops Clocked flip-flops are sometimes referred to as registers, although technically speaking, a register is a bank of several flip-flops with a common clock signal. Unclocked Flip-Flops Latches - Latches An - latch can be built out of NO gates as shown in Figure, and behaves according to the truth table in Table 9. stands for set and stands for reset, as suggested by the truth table. Note that the latch actually has two outputs, which are complementary. These are referred to as and. If both and are raised at the same time, then both and will be HlGH; although this is physically possible, it does not make sense if and are to be complementary signals. Thus, this condition is not allowed. Logic eference Guide 6-

10 Figure. An - Latch 9A-9 There are some applications where it is desirable for the input data to be effective only when another signal usually called a control signal is active. The circuit of Figure can be modified to give an - latch with a control input, as shown in Figure 13. The operation of this circuit is summarized in Table and Figure 14. The - latch is somewhat restrictive, since both inputs cannot be HIGH at the same time. The other latch types are based on the - latch, but have additional logic which removes the input restrictions. Table 9. - Latch Truth Table Not allowed The transfer function for this latch can be derived with a arnaugh map, as shown in Figure. By choosing either 1 s or 0 s, we can obtain two representations: a. + = +/* b. /+ = +/*/ Figure Latch Behavior 9A- C C X X X X 9A Figure 13. Adding a Control Input to an - Latch + 9A- /+ a. + = + /* b. /+ = + /*/ Figure. arnaugh Map for an - Latch Waveforms illustrating the operation of the - latch are shown in Figure 12. Table. Truth Table for an - Latch with a Control Input C + X X Not allowed 6-12 Logic eference Guide

11 C 9A-13 Figure 14. Behavior of an - Latch with a Control Input -Type Latches (Transparent Latches) A single-input latch can be formed by adding some logic to the controlled - latch in Figure 13; this gives rise to the -type latch in Figure 15. This latch is often called a transparent latch, since data on the input passes right through to the output as long as the control input is HlGH. If the control input is set LOW, then the latch holds whatever data was present when the control went LOW. With this type of latch, the control is usually called a gate. G 9A-15 The behavior of the -type latch is shown in Table and Figure 16. The basic transfer function for a -type latch can be derived from the arnaugh map in Figure 17. Figure 16. -Type (Transparent) Latch Behavior + = *G + */G /+ = /*G + /*/G G G G C G A Figure 15. A -Type (Transparent) Latch Table. Truth Table for a -Type Latch G + X /+ a. + = *G + */G b. /+ = /*G + /*/G 9A-16 Figure 17. arnaugh Maps for a -Type Latch Logic eference Guide 6-13

12 If realized exactly as the transfer function indicates, the result is actually a glitchy circuit. - Latches Another two-input latch can be derived from the - latch as shown in Figure 18. This is called a - latch, and operates in the same manner as an - latch, except that the condition where both inputs are HIGH is now allowed. The truth table is shown in Table 12; the waveforms are shown in Figure 19. Figure 18. A - Latch Table 12. Truth Table for a - Latch A-17 There are still some potential problems here for the case where and are both HIGH. If and are left HIGH for too long, the output may change more than one time; if left HIGH forever, the output will oscillate. Thus, and should not be asserted for a time longer than the propagation delay of the latch. There are also potential race conditions if and are not asserted and removed at exactly the same time. If one of the inputs is raised slightly ahead of the other, it may give the output time to react, giving the wrong output once the second input is raised. The same problem can occur if one input is lowered slightly before the other. This is illustrated in Figure 20. There are several ways to derive transfer functions for - latches. Two can be derived directly from arnaugh maps, as shown in Figure 21; the others are not as obvious, and make use of the XO gate described before. The basic transfer functions are listed in Table 13. Table 13. Transfer Functions for a - Latch + = * / /+ = /* / + /* + * + = /+ = / :+: (* / :+: (*/ + *) + *) + = / /+ = :+: (/*/ :+: (/*/ + /*) + /*) 9A-18 Figure 19. Behavior of a - Latch 6-14 Logic eference Guide

13 δτ δτ a. Falling Edge ace Conditions Expected Levels δτ δτ b. ising Edge ace Conditions Expected Levels tp OF Latch c. Possible Oscillation 9A-19 Figure 20. Hazards Inherent in a - Latch Logic eference Guide 6-15

14 T T A Figure 22. A T-Type Latch Table 14. The Truth Table for a T-Type Latch + /+ a. + = */ + /* b. /+ = /*/ + * Figure 21. arnaugh Maps for a - Latch 9A-20 T-Type Latches T-type latches are formed by connecting the and inputs of a - latch together to form a single input, as shown in Figure 22. This latch has two possible functions: hold the present state or invert the output, as summarized in Table 14. T stands for trigger or toggle depending on who you talk to. That is, when T is HIGH, a change at the output is triggered; or, put another way, raising T causes the output to toggle. T / This Latch also has the problem that if T is left HIGH for too long, the output will oscillate. However, since there is only one input, the race condition problems of the - latch have been eliminated. Unfortunately, this comes at the cost of initialization. There is now no way to get the output into a fixed state without knowing what the previous state was. Thus, this device is not very useful without some kind of initialization circuit. The general waveforms for a T-type latch are shown in Figure 23. T tp OF Latch 9A-22 Figure 23. Behavior of a T-Type Latch 6-16 Logic eference Guide

15 From the arnaugh map in Figure 24, we can generate the following transfer functions: + = T*/ /+ = T* + /T* + /T*/ AM Clocked Flip-Flops Latches can be modified by adding a clock input. The purpose of the clock is to delay any output changes until the clock signal changes. Whereas latch control inputs (such as the gate) are level-sensitive, clock inputs are generally edge-sensitive (or edge-triggered), meaning that output transitions can occur only when a clock transition is detected. A device is classified as positive edge-triggered or negative edge-triggered, depending on whether it responds to the rising or falling edge of the clock signal, respectively. The behavior to a clocked - flip-flop is illustrated in Figure 25. T + = :+:T /+ = / :+: T + = /:+: /T /+ = :+: /T T /+ a. + = T*/ + /T* b. /+ = T* + /T*/ 9A-23 The clock provides two basic advantages. It removes the hazards inherent in the - and T flip-flops, since all inputs will have settled by the time the clock edge arrives, and only one transition is possible for each clock edge. The clock also allows the design of synchronous systems, where all signals are coordinated with other signals. The entire system is then regulated by the clock. The basic behavior of the four flip-flops types does not change with the addition of a clock; the output changes are merely made to wait for the clock edge. Thus, the basic transfer equations for most of the flip-flops are the same. We can indicate the clocked nature of the flipflops by using the registered assignment := instead of =. Figure 24. arnaugh Maps for a T-Type Latch -Type Flip-Flops This is the only flip-flop type whose basic transfer characteristic changes, because the clock input replaces the gate input. Thus the transfer equations become: +:= /+ := / That is, whatever data appears on the input will be transferred to the output after the next clock edge. The input is not changed in any way. Logic eference Guide 6-17

16 The simplicity of this flip-flop makes it the most widely used flip-flop. However, functions are sometimes more conveniently expressed using - flip-flops, or using T-type flip-flops. If we replace the signal with the transfer function for one of the other flip-flop types, we can then emulate that flip-flop type in the -type flip-flop. This is equivalent to taking a latch and placing a clocked -type flip-flop after the latch output for synchronization. Figure 26 illustrates how each flip-flop can be emulated in a -type flip-flop. The standard schematic symbols for the flip-flop types are also shown. Table 15 summarizes the transfer functions for all of the flip-flop types. These functions can directly be used to emulate a particular flip-flop type in a -type flip-flop. This can be particularly useful since -type flip-flops are available in most registered PLs. Clock p n 9A-24 Figure 25. Behavior of a Clocked - Flip-Flop for Positive (p) and Negative (n) Edge-Triggered - Flip-Flops 6-18 Logic eference Guide

17 Clock a. Clocked -Type Flip-Flop Clock b. Clocked - Flip-Flop T T T Clock c. Clocked T-Type Flip-Flop T Clock d. Clocked - Flip-Flop 9A-25 Figure 26. Clocked Flip-Flops. All can be Emulated with a -Type Flip-Flop Logic eference Guide 6-19

18 Table 15. Clocked Flip-Flop Transfer Functions -Type + := /+ := / + := */ /+ := /* / + /* + * + := /+ := / --Type :+: (*/ :+: (*/ + *) + *) + := / /+ := :+: (/*/ :+: (/*/ + /*) + /*) + := T*/ /+: = T*/ + /T* + /T*/ T-Type + := :+:T /+ := / :+: T + := / :+: /T /+ := :+: /T --Type + := /+ := + /* + /*/ Binary Numbers The concept of a number is taken for granted by most people. And most people equate numbers in general with the decimal system, with which we are most familiar. However, there is nothing particularly special about the decimal system; the choice of system is actually rather arbitrary. History has chosen the decimal system for most humans. For electronic systems, the binary system is more appropriate. It makes possible arithmetic and logical calculations that would be much more difficult likely impractical if implemented directly in a decimal system. Closely related to the binary system are the octal and hexadecimal systems, which will also be discussed here. Arithmetic is normally performed using binary numbers in a computer. Octal and hexadecimal representations are generally used as a way to abbreviate what might otherwise be lengthy binary numbers. This will be seen when conversion is discussed below. There are several terms which must be defined before proceeding further. A number is an abstract entity which is used to describe quantity. There are many ways of representing a number. Normally, the representation is designed around a base. The number is expressed as a sum of multiples of the powers of the base. The decimal system is a base- system, meaning that is used as the base. The binary system is base-2; the octal system is base-8; and the hexadecimal system is base-16. The binary, octal, and hexadecimal systems are closely related because 8 and 16 are both powers of 2. When different bases are being used, a number will often be followed by its base in subscript, to indicate exactly what the base is. For example, the decimal number 25 would be written 25 if its base were in doubt. A number can thus be expressed in terms of some base x as follows: anx n +an-1x n a1x 1 +a0x 0 +a 1x a mx m (1) The numbers an...a m are called digits. The value of each digit can range from 0 to x 1. Each digit is represented by a symbol, called a numeral. X numerals are required to represent a number in base x. The most familiar numerals are the symbols 0, 1, There are ten of them, since they are used for the decimal system. For binary numbers, only 0 and 1 are used; for octal numbers, the numerals 0 through 7 are used. Hexadecimal numbers are more difficult, since sixteen numerals are required. Therefore, the numerals 0 through 9 are used to represent the quantities 0 through 9; the letters A through F are used to represent the quantities through 15. The number expressed by equation 1 is normally represented as a string of digits: anan 1...a1a0.a 1...a m The digits representing negative powers of the base are separated from those representing non-negative powers by a point. In the decimal system, this is referred to as a decimal point; in the binary system, it is referred to as a binary point. There are two basic classes of manipulation which will be discussed: conversions between bases and arithmetic within a base Logic eference Guide

19 Converting Between Bases Base-2 < > Base- Converting a binary number to a decimal number is accomplished by using equation 1 directly. Example: Converting.02 to decimal: Y =.0 = = = When converting whole numbers from decimal to binary, the decimal number is repeatedly divided by 2. Integer division is used, so the quotients are rounded down to the next integer. The remainders form the digits of the number. The least significant digit is the first one calculated. Example: Converting 60 to binary: 61/2 = 30 remainder = 1 LB 30/2 = 15 remainder = 0 15/2 = 7 remainder = 1 7/2 = 3 remainder = 1 3/2 = 1 remainder = 1 1/2 = 0 remainder = 1 MB 60 =2 When converting a decimal fraction into a binary fraction, the decimal number is multiplied by 2. This results in a whole number and a fraction. The whole number is a digit; the procedure is repeated on the new fraction. This procedure is repeated until the fractional portion is zero. If the procedure does not terminate, then the result is a repeating fraction. The first digit calculated is the most significant digit. Example: Converting.1625 to binary: = whole portion = 0 MB = 0.65 whole portion = = 1.3 whole portion = = 0.6 whole portion = = 1.2 whole portion = = 0.4 whole portion = = 0.8 whole portion = = 1.6 whole portion = = 1.2 whole portion = 1 AM Here we see that the fraction will repeat, since we have already multiplied 0.6 earlier. Thus = For mixed numbers, it is necessary to calculate the whole and fractional portions separately. Thus, for example, we know that = These are actually general procedures which can be used to convert a decimal number into any base, and vice versa. Examples: 1. Converting to decimal: Y = = = = Converting to octal: 6/8 = 13 remainder = 2 LB 13/8 = 1 remainder = 5 1/8 = 0 remainder = 1 MB Thus, the whole portion is = 0.83 whole portion = 0 MB = 6.64 whole portion = = 5.12 whole portion = = 0.96 whole portion = = 7.68 whole portion = = 5.44 whole portion = 5 At this point we have enough significant digits. We could continue either until the procedure terminated, or until the pattern started repeating. However, those last digits are not likely to be significant. Thus, we can approximate by saying that = Converting 31F.A216 to decimal: Y = 31F.A216 = = = F.A216 = Converting to hexadecimal: 7689/16 = 480 remainder = 9 LB 480/16 = 30 remainder = 0 30/16 = 1 remainder = E 1/16 = 0 remainder = 1 MB Logic eference Guide 6-21

21 This eight-bit code allows us to represent the numbers from 127 to When performing addition with one s complement numbers, it is important to watch for overflow results. Whenever an overflow occurs, a correction must be made by adding 1 to the result. In some cases, the results of an operation will not be meaningful, since the intended result cannot be represented. For instance, in the eight-bit system above, adding 127 to 127 will give a meaningless result, since 254 cannot be represented in this system. Thus, the operation must be evaluated to ensure that the result is meaningful. Examples: All examples will use 4-bit systems. Thus, the range of representable numbers is from 7 to +7. AM Add 3 + 2: result meaningful Add (14 cannot be represented): result meaningless ubtract 3 from 7: overflow add 1, +1 discard overflow 4 bit ubtract 5 from 2: result meaningful ubtract 6 from 5 ( cannot be represented): overflow add 1, +1 discard overflow bit 4 result meaningless ubtract 5.25 from 3.5 (fixed point; requires 6 bits): result meaningful ubtract 7 from 7: one of the representations of 0 Logic eference Guide 6-23

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