ECE124 Digital Circuits and Systems Page 1


 Bertina Fitzgerald
 2 years ago
 Views:
Transcription
1 ECE124 Digital Circuits and Systems Page 1
2 Chip level timing Have discussed some issues related to timing analysis. Talked briefly about longest combinational path for a combinational circuit. Talked briefly about timing with flipflops; i.e., Data input must be stable before active clock edge (setup time). Data input must be stable after active clock edge (hold time). Data output doesn t change immediately after the active clock edge (clocktooutput time). When we build an entire circuit (one with both flipflops and combinational logic), there are other important timing concepts to understand. ECE124 Digital Circuits and Systems Page 2
3 Cycle times (1) Consider flipflop outputs being used to generate flipflop inputs: Tco Tdata Tsu clk combinatorial D Q D Q logic (and delay) Tclk1 Tclk2 It takes time for signals to arrive where they need to be ECE124 Digital Circuits and Systems Page 3
4 Cycle times (2) Sequence of events in transfer of data between flipflops : Takes time for active clock edge to arrive at first FF (Tclk1). Once active clock edge arrives, takes time for output of first FF to change (+Tco). Takes time for output of first FF to cause changes in the input value to the second FF due to combinatorial logic between FF (+Tdata). Input at second FF must be present prior to active clock edge at second FF (Tsu). Takes time for clock to arrive at second FF (Tclk2). Must be some limit of how fast we can clock the circuit (i.e., the frequency of clock signal): Data output from first FF must get to data input of second FF prior to the next active clock edge. ECE124 Digital Circuits and Systems Page 4
5 Cycle times (3) For the data output of the first FF to get to the data input of the second FF in sufficient time, the following must be true: The minimum period (maximum frequency) of the circuit is: ECE124 Digital Circuits and Systems Page 5
6 Cycle times (4) Tco Tdata Tsu clk combinatorial D Q D Q logic (and delay) Tclk1 Tclk2 The equation for Tcycle tells us a minimum clock period (or maximum frequency) at which our circuit can operate without violating the setup time at the second FF input. ECE124 Digital Circuits and Systems Page 6
7 Cycle times (5) Tclk1 Tco Tdata Tsu CLK FF1 CLK FF2 CLK FF1 Q FF2 D Tclk1 Tcycle ECE124 Digital Circuits and Systems Page 7
8 Clock skew If we look at our equation for maximum frequency: Circuit frequency <= 1/Tcycle The term (Tclk1 Tclk2) that measures the difference in time between the arrival of the active clock edge at the two flipflops. This difference is called clock skew and it can be positive or negative. In general, clock skew is a big hassle, and we would like to avoid it if possible. ECE124 Digital Circuits and Systems Page 8
9 Inverted clocks (1) Sometimes we might have flipflops clocked on different edges of the clock; some flipflops trigger on the rising edge and others on the falling edge. This can limit the maximum frequency of the circuit too since we have less time to get data to where it needs to be! Tco Tdata Tsu clk combinatorial D Q D Q logic (and delay) Tclk1 Tclk2 Rising edge Falling edge ECE124 Digital Circuits and Systems Page 9
10 Inverted clocks (2) Tclk1 Tco Tdata Tsu CLK FF1 CLK FF2 CLK FF1 Q FF2 D Tclk1 Tcycle Since the second FF is triggered on the falling edge, either Tdata must be short enough, or the cycle time for the clock needs to be lengthened (lower frequency) to allow the data to get to the second FF. ECE124 Digital Circuits and Systems Page 10
11 Tclk1 Tco Tdata Tsu CLK FF1 CLK FF2 CLK FF1 Q FF2 D Tclk1 Tcycle ECE124 Digital Circuits and Systems Page 11
12 Duty cycles Sometimes the clock signal is not symmetric; It has a nonuniform duty cycle. If we use both rising and falling edge triggering, this can also affect the clock frequency. 2/3 high (66% duty cycle) CLK 1/3 low ECE124 Digital Circuits and Systems Page 12
13 Setup and hold times at the pins of a chip (1) Say we have a circuit implemented inside of an integrated circuit (IC) chip. The circuit and IC now looks like a blackbox. Timing at the pins of the chip are now important. Suppose you have a data present at at input pin on the IC. The signal might go through some logic inside the IC prior to reaching a flipflop input inside of the IC. The flipflop inside of the IC is clocked by another clock signal applied at another pin of the IC. ECE124 Digital Circuits and Systems Page 13
14 Setup and hold times at the pins of a chip (2) There is a setup and hold time at the flipflop inside of the IC and a relationship between the FFD input and the FFCLK input. Therefore, there must be a relationship between the data input and the clock input at the chip pins. data Tdata Tsu combinatorial logic (and delay) Tsu/Th D Q clk pins at IC boundary Tclk logic inside IC flipflop inside IC ECE124 Digital Circuits and Systems Page 14
15 Setup and hold times at the pins of a chip (3) Let: cf  time when active clock edge arrives at FF CLK INPUT. cc  time when active clock edge arrives at CLK PIN. df  time when data input at FF D INPUT makes a transition. dc  time when data input at DATA PIN makes a transition. Let: Tsu  the setup time of the FF D input w.r.t. the FF CLK input. Th  the hold time of the FF D input w.r.t. the FF CLK input. Let: Tsetup  the setup time of the DATA PIN input w.r.t. the CLK PIN. Thold  the hold time of the DATA PIN input w.r.t. the CLK PIN. ECE124 Digital Circuits and Systems Page 15
16 Setup and hold times at the pins of a chip (4) The following must be true at the flipflop: df not in [cftsu,cf+th] otherwise the flipflop might not work correctly (data must be stable around the active clock edge). Two inequalities: df not in [cftsu,cf+th] implies: df not in [cftsu,cf+th] implies: df < cf Tsu dc+tdata = df cc + Tclk = cf dc+tdata < cc+tclktsu but: and: so: and: df > cf + Th dc+tdata = df cc + Tclk = cf dc+tdata > cc+tclk+th but: and: so: and: dc < cc (TsuTclk+Tdata). df can occur here Recall: cf  time when active clock edge arrives at FF CLK INPUT. cc  time when active clock edge arrives at CLK PIN. df  time when data input at FF D INPUT makes a transition. dc  time when data input at DATA PIN dc+tdata makes a transition. dc > cc + (Th+TclkTdata). cc cftsu Tsu cf cc+tclk ECE124 Digital Circuits and Systems Page 16
17 Setup and hold times at the pins of a chip (5) We find a relationship between the data input and clock input at the IC PINS due to the relationship at the FF inputs inside the chip: dc < cc (TsuTclk+Tdata). dc > cc + (Th+TclkTdata). So, we have the relationship: dc not in [cctsetup,cc+thold] There are setup and hold times at the IC inputs. When we use an IC, we must pay attention to these times to make sure that the IC will work correctly. ECE124 Digital Circuits and Systems Page 17
18 Setup and hold times at the pins of a chip (6) data Tdata Tsu combinatorial logic (and delay) Tsu/Th D Q clk Tseup Thold Tsu Th pins at IC boundary Tclk logic inside IC flipflop inside IC Tclk CLK FF CLK FF D DATA Tdata Tdata ECE124 Digital Circuits and Systems Page 18
19 Setup and hold times at the pins of a chip (7) When active clock edge arrives at a FF CLK input, the FF Q output changes after Tco. Consider that the FF Q output drives OUTPUT PIN of IC. Output will not appear for an amount of time called CLOCKTOOUTPUT TIME. Tdata clk D Tco Q combinatorial logic (and delay) data Tclk pins at IC boundary flipflop inside IC logic inside IC Tclock_to_output = Tclk + Tco + Tdata ECE124 Digital Circuits and Systems Page 19
20 Setup and hold times at the pins of a chip (8) Tdata clk D Tco Q combinatorial logic (and delay) data Tclk Tco Tdata Tclk pins at IC boundary flipflop inside IC logic inside IC CLK FF CLK FF D FF Q DATA ECE124 Digital Circuits and Systems Page 20
21 Implementing logic gates in CMOS Logic gates are implemented via transistors. One popular technology for implementing transistors is Complementary Metal Oxide Semiconductor (CMOS) technology. Transistors effectively implement switches. There are two types of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), namely the nchannel (NMOS) and p channel (PMOS) transistor. CMOS uses both NMOS and CMOS transistors to implement logic gates in a complementary way. ECE124 Digital Circuits and Systems Page 21
22 Voltages and logic levels Logic levels are represented with voltages. The logic level 0 is represented by the lowest voltage (GND) The logic level 1 is represented by the highest voltage (VDD) Transistors are used as switches to open or close and connect wires to either VDD or GND. ECE124 Digital Circuits and Systems Page 22
23 NMOS transistor Simplified NMOS transistor has 3 terminals: 1) the Gate (G); 2) the Source (S) and 3) the Drain (D). The source is at a lower voltage; The drain is at a higher voltage. When a high voltage is applied to G (w.r.t. to S) and V GS is above some threshold voltage V T the switch closes and D is connected to S (current flows from D to S). This pulls down the voltage at D to the voltage at S. When the voltage between G and S is less than some threshold voltage V T the switch opens and D is disconnected from S (no current flows from D to S). ECE124 Digital Circuits and Systems Page 23
24 PMOS transistor Simplified PMOS transistor has 3 terminals: 1) the Gate (G); 2) the Source (S) and 3) the Drain (D). The source is at a higher voltage; The drain is at a lower voltage. When a low voltage is applied to G (w.r.t. to S) and V SG is above some threshold voltage V T the switch closes and S is connected to D (current flows from S to D). This pulls up the voltage at D to the voltage at S. When the voltage between S and G is less than some threshold voltage V T the switch opens and S is disconnected from D (no current flows from S to D). ECE124 Digital Circuits and Systems Page 24
25 CMOS structure CMOS combines NMOS and PMOS transistors in a structure which consists of a PullUp Network (PUN) and a PullDown Network (PDN) to implement logic functions. PUN and PDN are duals of each other. g A current path (connection) from V DD to V F means V F is high (f is logic 1) A current path (connection) from V F to GND means V F is low (f is logic 0).!f AND corresponds to transistors in series OR corresponds to transistors in parallel ECE124 Digital Circuits and Systems Page 25
26 CMOS inverter When V X is high (logic 1): 1) NMOS is closed; 2) PMOS is open;3) current flows from V F to GND V F is GND (logic 0). When V X is low (logic 0): 1) NMOS is open; 2) PMOS is closed;3) current flows from V DD to V F V F is V DD (logic 1). ECE124 Digital Circuits and Systems Page 26
27 CMOS NAND!x +!y 4 transistors!(xy) ECE124 Digital Circuits and Systems Page 27
28 CMOS NOR!x!y!(x+y) 4 transistors ECE124 Digital Circuits and Systems Page 28
29 CMOS AND Uses a CMOS NAND followed by a CMOS inverter 6 transistors ECE124 Digital Circuits and Systems Page 29
30 What s this? A B C V0o ut Vdd Vdd Vdd Vdd Vdd Gnd Gnd Gnd ECE124 Digital Circuits and Systems Page 30
31 Transmission gates When S is high (!S is low), both NMOS and PMOS are closed f = x. When S is low (!S is high), both NMOS and PMOS are open f is disconnected from x (high impedence). ECE124 Digital Circuits and Systems Page 31
32 XOR (using transmission gates) 8 transistors ECE124 Digital Circuits and Systems Page 32
Logic Design. Implementation Technology
Logic Design Implementation Technology Outline Implementation of logic gates using transistors Programmable logic devices Complex Programmable Logic Devices (CPLD) Field Programmable Gate Arrays (FPGA)
More informationChapter 10 Advanced CMOS Circuits
Transmission Gates Chapter 10 Advanced CMOS Circuits NMOS Transmission Gate The active pullup inverter circuit leads one to thinking about alternate uses of NMOS devices. Consider the circuit shown in
More informationPassTransistor Logic. Topics. NMOSOnly Logic. PassTransistor Logic. Resistance of Transmission Gate. PassTransistor Logic.
Topics Transmission Gate Passtransistor Logic 3 March 2009 1 3 March 2009 2 NMOSOnly Logic Example: AND Gate 3 March 2009 3 3 March 2009 4 Resistance of Transmission Gate XOR 3 March 2009 5 3 March 2009
More informationEEC 116 Lecture #6: Sequential Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #6: Sequential Logic Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 3 extended, same due date as Lab 4 HW4 issued today Amirtharajah/Parkhurst,
More informationBasic CMOS concepts. Computer Design and Technology Assignment 2
Basic CMOS concepts We will now see the use of transistor for designing logic gates. Further down in the course we will use the same transistors to design other blocks (such as flipflops or memories)
More information3. Implementing Logic in CMOS
3. Implementing Logic in CMOS 3. Implementing Logic in CMOS Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 26 August 3, 26 ECE Department,
More informationChapter 8. O.C., Tristate AND TRISTATE GATES
Chapter 8 O.C., Tristate AND TRISTATE GATES Lesson 3 Tristate Gate Outline Tristate gate circuit Tristate gate features Tristate gate applications Definition Tristate means a state of logic other than
More informationCMOS Digital Circuits
CMOS Digital Circuits Types of Digital Circuits Combinational The value of the outputs at any time t depends only on the combination of the values applied at the inputs at time t (the system has no memory)
More information3. Implementing Logic in CMOS
3. Implementing Logic in CMOS Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2016 August 31, 2016 ECE Department, University of Texas
More information10.3 CMOS Logic Gate Circuits
11/14/2004 section 10_3 CMOS Logic Gate Circuits blank.doc 1/1 10.3 CMOS Logic Gate Circuits Reading ssignment: pp. 963974 Q: Can t we build a more complex digital device than a simple digital inverter?
More informationLogic Gates & Operational Characteristics
Logic Gates & Operational Characteristics NOR Gate as a Universal Gate The NOR gate is also used as a Universal Gate as the NOR Gate can be used in a combination to perform the function of a AND, OR and
More informationPrinciples of VLSI Review. CMOS Transistors (Ntype)
Principles of VSI Review Static CMOS ogic Design Delay Models Power Consumption CMOS Technology Scaling R 9/00 1 g s CMOS Transistors (Ntype) Ntype (NMOS) transistor  can think of it as a switch. g:
More informationComputer Systems Lab 1. Basic Logic Gates
Computer Systems Lab Basic Logic Gates Object To investigate the properties of the various types of logic gates, and construct some useful combinations of these gates. Parts () 700 Quad input NAND gate
More informationCombinational Logic Building Blocks and Bus Structure
Combinational Logic Building Blocks and Bus Structure ECE 5A Winter 0 Reading Assignment Brown and Vranesic Implementation Technology.8 Practical Aspects.8.7 Passing s and 0s Through Transistor Switches.8.8
More informationNMOS Digital Circuits. Introduction Static NMOS circuits Dynamic NMOS circuits
NMOS Digital Circuits Introduction Static NMOS circuits Dynamic NMOS circuits Introduction PMOS and NMOS families are based on MOS transistors with induced channel of p, respectively n NMOS circuits mostly
More informationHere we introduced (1) basic circuit for logic and (2)recent nanodevices, and presented (3) some practical issues on nanodevices.
Outline Here we introduced () basic circuit for logic and (2)recent nanodevices, and presented (3) some practical issues on nanodevices. Circuit Logic Gate A logic gate is an elemantary building block
More informationIndex i xi xv xxvi. Abstract List of Tables List of Figures Glossary. Page.No CHAPTER 1 INTRODUCTION
iv Abstract List of Tables List of Figures Glossary Index i xi xv xxvi CHAPTER 1 INTRODUCTION 1.1 Introduction 1.2 Formulation of the problem 1.3 Objectives 1.4 Methodology 1.5 Contribution of the Thesis
More informationSemiconductor Memories
Chapter 8 Semiconductor Memories (based on Kang, Leblebici. CMOS Digital Integrated Circuits 8.1 General concepts Data storage capacity available on a single integrated circuit grows exponentially being
More informationChapter 02 Logic Design with MOSFETs
Introduction to VLSI Circuits and Systems 路 論 Chapter 02 Logic Design with MOSFETs Dept. of Electronic Engineering National ChinYi University of Technology Fall 2007 Outline The Fundamental MOSFETs Ideal
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NORgate C = NOT (A or B)
Introduction to TransistorLevel Logic Circuits Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed state
More informationLecture 31. Inverters and Combinational Logic
Lecture 3 Konstantinos Masselos Department of Electrical & Electronic Engineering Imperial College London URL: http://cas.ee.ic.ac.uk/~kostas Email: k.masselos@imperial.ac.uk Lecture 31 Based on slides/material
More informationModule 4 : Propagation Delays in MOS Lecture 20 : Analyzing Delay in few Sequential Circuits
Module 4 : Propagation Delays in MOS Lecture 20 : Analyzing Delay in few Sequential Circuits Objectives In this lecture you will learn the delays in following circuits Motivation Negative DLatch SR Latch
More informationFOUR BIT SHIFT REGISTER
FOUR BIT SHIFT REGISTER EE 584 GUIDED BY: Dr. Elias Adjunct Professor University of Kentucky SUBMITTED BY: Chris Soh Karan Jhavar Stephen Disney Tapan Desai (Group 13) 1 INDEX Introduction..2 Historical
More informationSample Final Exam FinalDay, FinalMonth, FinalYear ELEC4708: Advanced Digital Electronics Department of Electronics, Carleton University
0 0 Sample Final Exam FinalDay, FinalMonth, FinalYear ELEC4708: Advanced Digital Electronics Department of Electronics, Carleton University Instructor: Maitham Shams Exam Duration: 3 hour Booklets: None
More informationDynamic Combinational Circuits
Dynamic Combinational Circuits Dynamic circuits Charge sharing, charge redistribution Domino logic npcmos (zipper CMOS) James Morizio 1 Dynamic Logic Dynamic gates use a clocked pmos pullup Two modes:
More informationWEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1
WEEK 8.1 egisters and Counters ECE124 igital Circuits and Systems Page 1 Additional schematic FF symbols Active low set and reset signals. S Active high set and reset signals. S ECE124 igital Circuits
More informationHaving read this workbook you should be able to: recognise the arrangement of NAND gates used to form an SR flipflop.
Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an SR flipflop. describe how such a flipflop can be SET and RESET. describe the disadvantage
More informationSlide Set 7. Latches and Clocking
Slide Set 7 Latches and Clocking Steve Wilton Dept. of ECE University of British Columbia stevew@ece.ubc.ca Slide Set 7 Page 1 Overview Reading: Wolf, Chapter 5 In this section, we will talk about charge
More informationinputs output Complementary CMOS Comlementary CMOS Logic Gates: nmos pulldown network pmos pullup network Static CMOS
Complementary CMOS Comlementary CMOS Logic Gates: nmos pulldown network pmos pullup network Static CMOS inputs pmos pullup network nmos pulldown network output Pullup O Pullup ON Pulldown O Z (float)
More informationCHAPTER 11: Flip Flops
CHAPTER 11: Flip Flops In this chapter, you will be building the part of the circuit that controls the command sequencing. The required circuit must operate the counter and the memory chip. When the teach
More informationSequential Logic. References:
Sequential Logic References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey, Prentice Hall UCB Principles of CMOS VLSI Design: A Systems Perspective, N. H. E. Weste, K. Eshraghian,
More informationBIPOLAR JUNCTION TRANSISTORS (BJTS)
BIPOLAR JUNCTION TRANSISTORS (BJTS) With an electrical current applied to the center layer (called the base), electrons will move from the Ntype side to the Ptype side. The initial small trickle acts
More informationC H A P T E R 14. CMOS Digital Logic Circuits
C H A P T E R 14 CMOS Digital Logic Circuits Introduction CMOS is by far the most popular technology for the implementation of digital systems. The small size, ease of fabrication, and low power consumption
More informationLayout of Multiple Cells
Layout of Multiple Cells Beyond the primitive tier primitives add instances of primitives add additional transistors if necessary add substrate/well contacts (plugs) add additional polygons where needed
More informationTiming Methodologies (cont d) Registers. Typical timing specifications. Synchronous System Model. Short Paths. System Clock Frequency
Registers Timing Methodologies (cont d) Sample data using clock Hold data between clock cycles Computation (and delay) occurs between registers efinition of terms setup time: minimum time before the clocking
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: March 29, 2016 Timing Hazards and Dynamic Logic Lecture Outline! Review: Sequential MOS Logic " SR Latch " DLatch! Timing Hazards! Dynamic
More informationAdvanced VLSI Design Combinational Logic Design
Combinational Logic: Static versus Dynamic Static: t every point in time (except during the switching transient), each gate output is connected to either V DD or V SS via a lowresistance path. Slower
More informationECE380 Digital Logic
ECE38 Digital Logic FlipFlops, egisters and Counters: Latches Dr. D. J. Jackson Lecture 24 torage elements Previously, we have considered combinational circuits where the output values depend only on
More informationElectronic Design Automation Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur
Electronic Design Automation Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture  10 Synthesis: Part 3 I have talked about twolevel
More informationLesson 12 Sequential Circuits: FlipFlops
Lesson 12 Sequential Circuits: FlipFlops 1. Overview of a Synchronous Sequential Circuit We saw from last lesson that the level sensitive latches could cause instability in a sequential system. This instability
More informationLayout Design and Simulation of CMOS Multiplexer
23 Layout and Simulation of CMOS Multiplexer Priti Gupta Electronics & Communication department National Institute of Teacher s Training and Research Chandigarh Rajesh Mehra Electronics & Communication
More informationSetReset (SR) Latch
eteset () Latch Asynchronous Level sensitive crosscoupled Nor gates active high inputs (only one can be active) + + Function 0 0 0 1 0 1 eset 1 0 1 0 et 1 1 0? 0? Indeterminate crosscoupled Nand gates
More informationDesign of a Low Power FourBit Binary Counter Using Enhancement Type Mosfet
Design of a Low Power FourBit Binary Counter Using Enhancement Type Mosfet Praween Sinha Department of Electronics & Communication Engineering Maharaja Agrasen Institute Of Technology, Rohini sector 22,
More informationDIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 5. LECTURE: SEQUENTIAL CIRCUITS BASICS AND FLIPFLOPS
DIGITAL TECHNICS Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 5. LECTURE: SEQUENTIAL CIRCUITS BASICS AND FLIPFLOPS 1st (Autumn) term 2014/2015 5. LECTURE 1. Sequential
More informationLatch Timing Parameters. Flipflop Timing Parameters. Typical Clock System. Clocking Overhead
Clock  key to synchronous systems Topic 7 Clocking Strategies in VLSI Systems Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Clocks help the design of FSM where
More informationSequential Circuits. Prof. MacDonald
Sequential Circuits Prof. MacDonald Sequential Element Review l Sequential elements provide memory for circuits heart of a state machine saving current state used to hold or pipe data data registers, shift
More informationElectronic Troubleshooting. Chapter 10 Digital Circuits
Electronic Troubleshooting Chapter 10 Digital Circuits Digital Circuits Key Aspects Logic Gates Inverters NAND Gates Specialized Test Equipment MOS Circuits FlipFlops and Counters Logic Gates Characteristics
More informationEnhancement Mode MOSFET Circuits
Engineering Sciences 154 Laboratory Assignment 4 Enhancement Mode MOSFET Circuits Note: This is quite a long, but very important laboratory assignment. Take enough time  at least two laboratory sessions
More informationCapacitors and RC Circuits
Chapter 6 Capacitors and RC Circuits Up until now, we have analyzed circuits that do not change with time. In other words, these circuits have no dynamic elements. When the behavior of all elements is
More informationLAB MANUAL SUBJECT: DIGITAL LOGIC DESIGN AND APPLICATIONS SE (COMPUTERS) SEM III
LAB MANUAL SUBJECT: DIGITAL LOGIC DESIGN AND APPLICATIONS SE (COMPUTERS) SEM III 1 INDEX Sr. No Title of the Experiment 1 Study of BASIC Gates 3 2 Universal Gates 6 3 Study of Full & Half Adder & Subtractor
More informationDigital VLSI design. Lecture 2: Complementary Metal Oxide Semiconductor (CMOS) Chips
Digital VLSI design Lecture 2: Complementary Metal Oxide Semiconductor (CMOS) Chips What will we learn? How integrated circuits work How to design chips with millions of transistors Ways of managing the
More informationLatches and FlipFlops characterestics & Clock generator circuits
Experiment # 7 Latches and FlipFlops characterestics & Clock generator circuits OBJECTIVES 1. To be familiarized with D and JK flipflop ICs and their characteristic tables. 2. Understanding the principles
More informationExperiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa
Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation
More information3 FlipFlops. The latch is a logic block that has 2 stable states (0) or (1). The RS latch can be forced to hold a 1 when the Set line is asserted.
3 FlipFlops Flipflops and latches are digital memory circuits that can remain in the state in which they were set even after the input signals have been removed. This means that the circuits have a memory
More informationCHAPTER 14 CMOS DIGITAL LOGIC CIRCUITS
CHAPTER 4 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 4. Digital Logic Inverters 4. The CMOS Inverter 4.3 Dynamic Operation of the CMOS Inverter 4.4 CMOS LogicGate Circuits 4.5 Implications of Technology
More informationLayout, Fabrication, and Elementary Logic Design
Introduction to CMOS VLSI Design Layout, Fabrication, and Elementary Logic Design Adapted from Weste & Harris CMOS VLSI Design Overview Implementing switches with CMOS transistors How to compute logic
More informationDC Noise Immunity of CMOS Logic Gates
DC Noise Immunity of CMOS Logic Gates Introduction The immunity of a CMOS logic gate to noise signals is a function of many variables, such as individual chip differences, fanin and fanout, stray inductance
More informationThe MOSFET Transistor
The MOSFET Transistor The basic active component on all silicon chips is the MOSFET Metal Oxide Semiconductor Field Effect Transistor Schematic symbol G Gate S Source D Drain The voltage on the gate controls
More informationPass Gate Logic An alternative to implementing complex logic is to realize it using a logic network of pass transistors (switches).
Pass Gate Logic n alternative to implementing complex logic is to realize it using a logic network of pass transistors (switches). Switch Network Regeneration is performed via a buffer. We have already
More information111. Stick Diagram and Lamda Based Rules
111 Stick Diagram and Lamda Based Rules Mask Layout (Print this presentation in colour if possible, otherwise highlight colours) 112 Circuit coloured mask layer layout Coloured stick diagram mask representation
More information9. Memory Elements and Dynamic Logic
9. Memory Elements and RS Flipflop The RSflipflop is a bistable element with two inputs: Reset (R), resets the output Q to 0 Set (S), sets the output Q to 1 2 RSFlipflops There are two ways to implement
More informationCMOS Power Consumption
CMOS Power Consumption Lecture 13 18322 Fall 2003 Textbook: [Sections 5.5 5.6 6.2 (p. 257263) 11.7.1 ] Overview Lowpower design Motivation Sources of power dissipation in CMOS Power modeling Optimization
More informationModule 4 : Propagation Delays in MOS Lecture 22 : Logical Effort Calculation of few Basic Logic Circuits
Module 4 : Propagation Delays in MOS Lecture 22 : Logical Effort Calculation of few Basic Logic Circuits Objectives In this lecture you will learn the following Introduction Logical Effort of an Inverter
More informationGates & Boolean Algebra. Boolean Operators. Combinational Logic. Introduction
Introduction Gates & Boolean lgebra Boolean algebra: named after mathematician George Boole (85 864). 2valued algebra. digital circuit can have one of 2 values. Signal between and volt =, between 4 and
More informationDIGITAL SYSTEM DESIGN LAB
EXPERIMENT NO: 7 STUDY OF FLIP FLOPS USING GATES AND IC S AIM: To verify various flipflops like D, T, and JK. APPARATUS REQUIRED: Power supply, Digital Trainer kit, Connecting wires, Patch Chords, IC
More informationStandard cell libraries are required by almost all CAD tools for chip design
Standard Cell Libraries Standard cell libraries are required by almost all CAD tools for chip design Standard cell libraries contain primitive cells required for digital design However, more complex cells
More informationECE 301 Digital Electronics
ECE 301 Digital Electronics Latches and FlipFlops (Lecture #18) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and
More informationLecture 10. Latches and FlipFlops
Logic Design Lecture. Latches and FlipFlops Prof. Hyung Chul Park & Seung Eun Lee Sequential Logic Outputs of sequential logic depend on current inputs and prior input values Sequential logic might explicitly
More informationLAB 7 MOSFET CHARACTERISTICS AND APPLICATIONS
LAB 7 MOSFET CHARACTERISTICS AND APPLICATIONS Objective In this experiment you will study the iv characteristics of an MOS transistor. You will use the MOSFET as a variable resistor and as a switch. BACKGROUND
More informationLatches, the D FlipFlop & Counter Design. ECE 152A Winter 2012
Latches, the D FlipFlop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 FlipFlops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR
More information! Logically, each transistor acts as a switch! Combined to implement logic functions (gates) n AND, OR, NOT
Computing Layers Chapter 3 Digital Logic Structures Problems Algorithms Language Instruction Set Architecture Microarchitecture Original slides from Gregory Byrd, North Carolina State University Modified
More informationLM555 Timer MOS Inverter MOSFET Analog Switch SampleandHold Amplifier 2:1 Analog Multiplexer
LM555 Timer MOS Inverter MOSFET Analog Switch SampleandHold Amplifier :1 Analog Multiplexer ECE 04 Lab 4 Objective The purpose of this lab is to gain familiarity with circuits that are useful in "mixedsignal"
More informationChapter 5 System Timing
LED Array Scope, Part 2 Chap 5: Page 1 L.E.D. Oscilloscope Learn Electronics by Doing  Theory is pretty thin stuff until it s mixed with experience. Chapter 5 System Timing To be able to sweep the dot
More informationEE4232 Review of BJTs, JFETs and MOSFETs
EE4232 Review of BJTs, JFETs and MOSFETs 0 A simplified structure of the npn transistor. 1 A simplified structure of the pnp transistor. 2 Current flow in an npn transistor biased to operate in the active
More informationAn astable multivibrator acts as an oscillator (clock generator) while a monostable multivibrator can be used as a pulse generator.
Concepts In sequential logic, the outputs depend not only on the inputs, but also on the preceding input values... it has memory. Memory can be implemented in 2 ways: Positive feedback or regeneration
More informationNTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter
NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter Description: The NTE2053 is a CMOS 8 bit successive approximation Analog to Digital converter in a 20 Lead DIP type package which uses a differential
More informationSo far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs.
equential Logic o far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs. In sequential logic the output of the
More informationLayout of Transmission Gate. 2input Multiplexer Layout
Layout of Transmission Gate S S input Multiplexer Layout 1 Chapter 5 CMOS logic gate design Section 5. To achieve correct operation of integrated logic gates, we need to satisfy 1. Functional specification.
More informationCHAPTER 16 Memory Circuits
CHAPTER 16 Memory Circuits Introduction! The 2 major logic classifications are! Combinational circuits: Their output depends only on the present value of the input. These circuits do not have memory.!
More informationSequential 4bit Adder Design Report
UNIVERSITY OF WATERLOO Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4bit Adder Design Report Prepared by: Ian Hung (ixxxxxx), 99XXXXXX Annette Lo (axxxxxx), 99XXXXXX Pamela
More informationGates and Logic: From switches to Transistors, Logic Gates and Logic Circuits
Gates and Logic: From switches to Transistors, Logic Gates and Logic Circuits Hakim Weatherspoon CS 3410, Spring 2013 Computer Science Cornell University See: P&H ppendix C.2 and C.3 (lso, see C.0 and
More informationBasic Logic Circuits
Basic Logic Circuits Required knowledge Measurement of static characteristics of nonlinear circuits. Measurement of current consumption. Measurement of dynamic properties of electrical circuits. Definitions
More informationEEC 118 Spring 2011 Midterm
EEC 118 Spring 2011 Midterm Rajeevan Amirtharajah Dept. of Electrical and Computer Engineering University of California, Davis May 2, 2011 This examination is closed book and closed notes. Some formulas
More informationComparison of power consumption of 4bit binary counters with various state encodings including gray and onehot codes
1 Comparison of power consumption of 4bit binary counters with various state encodings including gray and onehot codes Varun Akula, Graduate Student, Auburn University, Dr. Vishwani D. Agrawal, James
More informationThe 555 timer: Waveform shaping
The 555 timer: Waveform shaping Introduction: Oscillators are ubiquitous not only in research environments but also in our modern, technologyoriented society. Oscillators are used for communication, timing
More informationBasics of Energy & Power Dissipation
Basics of Energy & Power Dissipation ecture notes S. Yalamanchili, S. Mukhopadhyay. A. Chowdhary Basic Concepts Dynamic power Static power Time, Energy, Power Tradeoffs Activity model for power estimation
More informationChapter 3 :: Sequential Logic Design
Chapter 3 :: Sequential Logic Design Digital Design and Computer Architecture David Money Harris and Sarah L. Harris Copyright 2007 Elsevier 3 Bistable Circuit Fundamental building block of other state
More informationEE 4432 VLSI Design Layout and Simulation of a 6T SRAM Cell
EE 4432 VLSI Design Layout and Simulation of a 6T SRAM Cell Mat Binggeli October 24 th, 2014 Overview Binggeli Page 2 The objective of this report is to describe the design and implementation of a 6transistor
More informationLecture 5: Gate Logic Logic Optimization
Lecture 5: Gate Logic Logic Optimization MAH, AEN EE271 Lecture 5 1 Overview Reading McCluskey, Logic Design Principles or any text in boolean algebra Introduction We could design at the level of irsim
More informationMOSFET transistor IV characteristics
MOSFET transistor IV characteristics Linear region: v DS «v GS Triode region: v DS < v GS i D = K[ 2( v GS )v DS ] 2 i D = K[ 2( v GS )v DS v DS ] K n K = = C ox µ n W  K 2L n v DS = v GS sat (current)
More informationNotes about Small Signal Model. for EE 40 Intro to Microelectronic Circuits
Notes about Small Signal Model for EE 40 Intro to Microelectronic Circuits 1. Model the MOSFET Transistor For a MOSFET transistor, there are NMOS and PMOS. The examples shown here would be for NMOS. Figure
More informationBidirectional level shifter for I²Cbus and other systems.
APPLICATION NOTE Bidirectional level shifter for I²Cbus and other Abstract With a single MOSFET a bidirectional level shifter circuit can be realised to connect devices with different supply voltages
More informationMultivibrator Circuits. Bistable multivibrators
Multivibrator ircuits Bistable multivibrators Multivibrators ircuits characterized by the existence of some well defined states, amongst which take place fast transitions, called switching processes. A
More informationClocking. Figure by MIT OCW. 6.884  Spring 2005 2/18/05 L06 Clocks 1
ing Figure by MIT OCW. 6.884  Spring 2005 2/18/05 L06 s 1 Why s and Storage Elements? Inputs Combinational Logic Outputs Want to reuse combinational logic from cycle to cycle 6.884  Spring 2005 2/18/05
More informationChapter 9 Latches, FlipFlops, and Timers
ETEC 23 Programmable Logic Devices Chapter 9 Latches, FlipFlops, and Timers Shawnee State University Department of Industrial and Engineering Technologies Copyright 27 by Janna B. Gallaher Latches A temporary
More informationDESIGN AND PERFORMANCE ANALYSIS OF CMOS FULL ADDER WITH 14 TRANSISTOR
DESIGN AND PERFORMANCE ANALYSIS OF CMOS FULL ADDER WITH 14 TRANSISTOR 1 Ruchika Sharma, 2 Rajesh Mehra 1 ME student, NITTTR, Chandigarh,India 2 Associate Professor, NITTTR, Chandigarh,India 1 just_ruchika016@yahoo.co.in
More informationBinary Adder. sum of 2 binary numbers can be larger than either number need a carryout to store the overflow
Binary Addition single bit addition Binary Adder sum of 2 binary numbers can be larger than either number need a carryout to store the overflow HalfAdder 2 inputs (x and y) and 2 outputs (sum and carry)
More informationNMOS Inverter. MOSFET Digital Circuits. Chapter 16. NMOS Inverter. MOSFET Digital Circuits
Chapter 16 MOSFET Digital Circuits In the late 70s as the era of LSI and VLSI began, NMOS became the fabrication technology of choice. Later the design flexibility and other advantages of the CMOS were
More informationENGR 210 Lab 10 RC Oscillators and Measurements Purpose: In a previous lab you measured the exponential response of RC circuits.
ENGR 210 Lab 10 RC Oscillators and Measurements Purpose: In a previous lab you measured the exponential response of RC circuits. Typically, the exponential time response of a circuit becomes important
More informationThe components. E3: Digital electronics. Goals:
E3: Digital electronics Goals: Basic understanding of logic circuits. Become familiar with the most common digital components and their use. Equipment: 1 st. LED bridge 1 st. 7segment display. 2 st. IC
More information