MOSFET MetalOxideSemiconductorFieldEffectTransistor. OptiMOS TM OptiMOS TM Power-MOSFET,40V BSC010N04LS. DataSheet. PowerManagement&Multimarket

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1 MOSFET MetalOxideSemiconductorFieldEffectTransistor OptiMOS TM OptiMOS TM PowerMOSFET,40V DataSheet Rev.2.2 Final PowerManagement&Multimarket

2 OptiMOS TM PowerMOSFET,40V 1Description Features Optimizedforsychronousrectification VerylowonresistanceRDS(on) %avalanchetested Superiorthermalresistance Nchannel,logiclevel QualifiedaccordingtoJEDEC 1) fortargetapplications Pbfreeleadplating;RoHScompliant HalogenfreeaccordingtoIEC Highersolderjointreliabilityduetoenlargedsourceinterconnection TDSON8FL(enlargedsourceinterconnection) Table1KeyPerformanceParameters Parameter Value Unit VDS 40 V RDS(on),max 1.0 mω ID A Qoss 84 nc Qg(0V..10V) 95 nc S 1 S 2 S 3 G 4 8 D 7 D 6 D 5 D Type/OrderingCode Package Marking RelatedLinks TDSON8 FL 010N04LS 1) JSTD20 and JESD22 2 Rev.2.2,

3 OptiMOS TM PowerMOSFET,40V TableofContents Description Maximum ratings Thermal characteristics Electrical characteristics Electrical characteristics diagrams Package Outlines Revision History Disclaimer Rev.2.2,

4 OptiMOS TM PowerMOSFET,40V 2Maximumratings attj=25 C,unlessotherwisespecified Table2Maximumratings Parameter Symbol Values Min. Typ. Max. Unit Note/TestCondition Continuous drain current ID Pulsed drain current 2) ID,pulse 400 A TC=25 C Avalanche current, single pulse 3) IAS 50 A TC=25 C 38 A VGS=10V,TC=25 C VGS=10V,TC= C VGS=4.5V,TC=25 C VGS=4.5V,TC= C VGS=10V,TA=25 C,RthJA=50K/W 1) Avalanche energy, single pulse EAS 330 mj ID=50A,RGS=25Ω Gate source voltage VGS V Power dissipation Ptot Operating and storage temperature Tj,Tstg C W TC=25 C TA=25 C,RthJA=50K/W 1) IEC climatic category; DIN IEC 681: 55/150/56 3Thermalcharacteristics Table3Thermalcharacteristics Values Parameter Symbol Unit Note/TestCondition Min. Typ. Max. Thermal resistance, junction case, bottom Thermal resistance, junction case, top RthJC K/W RthJC 20 K/W Device on PCB, 6 cm 2 cooling area 1) RthJA 50 K/W 1) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. 2) See figure 3 for more detailed information 3) See figure 13 for more detailed information 4 Rev.2.2,

5 OptiMOS TM PowerMOSFET,40V 4Electricalcharacteristics Table4Staticcharacteristics Parameter Symbol Values Min. Typ. Max. Unit Note/TestCondition Drainsource breakdown voltage V(BR)DSS 40 V VGS=0V,ID=1mA Gate threshold voltage VGS(th) V VDS=VGS,ID=250µA Zero gate voltage drain current IDSS µa VDS=40V,VGS=0V,Tj=25 C VDS=40V,VGS=0V,Tj=125 C Gatesource leakage current IGSS 10 na VGS=20V,VDS=0V Drainsource onstate resistance RDS(on) Gate resistance 1) RG Ω mω VGS=4.5V,ID=50A VGS=10V,ID=50A Transconductance gfs S VDS >2 ID RDS(on)max,ID=50A Table5Dynamiccharacteristics Values Parameter Symbol Unit Note/TestCondition Min. Typ. Max. Input capacitance 1) Ciss pf VGS=0V,VDS=20V,f=1MHz Output capacitance 1) Coss pf VGS=0V,VDS=20V,f=1MHz Reverse transfer capacitance 1) Crss pf VGS=0V,VDS=20V,f=1MHz Turnon delay time td(on) 10 ns Rise time tr 12 ns Turnoff delay time td(off) 46 ns Fall time tf 9 ns VDD=20V,VGS=10V,ID=30A, RG,ext,ext=1.6Ω VDD=20V,VGS=10V,ID=30A, RG,ext,ext=1.6Ω VDD=20V,VGS=10V,ID=30A, RG,ext,ext=1.6Ω VDD=20V,VGS=10V,ID=30A, RG,ext,ext=1.6Ω 1) Defined by design. Not subject to production test 5 Rev.2.2,

6 OptiMOS TM PowerMOSFET,40V Table6Gatechargecharacteristics 1) Parameter Symbol Values Min. Typ. Max. Unit Note/TestCondition Gate to source charge Qgs 16 nc VDD=20V,ID=50A,VGS=0to10V Gate charge at threshold Qg(th) 11 nc VDD=20V,ID=50A,VGS=0to10V Gate to drain charge 2) Qgd nc VDD=20V,ID=50A,VGS=0to10V Switching charge Qsw 21 nc VDD=20V,ID=50A,VGS=0to10V Gate charge total 2) Qg nc VDD=20V,ID=50A,VGS=0to10V Gate plateau voltage Vplateau 2.4 V VDD=20V,ID=50A,VGS=0to10V Gate charge total 2) Qg nc VDD=20V,ID=50A,VGS=0to4.5V Gate charge total, sync. FET Qg(sync) 84 nc VDS=0.1V,VGS=0to10V Output charge 2) Qoss nc VDD=20V,VGS=0V Table7Reversediode Parameter Symbol Values Min. Typ. Max. Unit Note/TestCondition Diode continuous forward current IS A TC=25 C Diode pulse current IS,pulse 400 A TC=25 C Diode forward voltage VSD V VGS=0V,IF=50A,Tj=25 C Reverse recovery time 2) trr ns VR=20V,IF=50A,diF/dt=400A/µs Reverse recovery charge Qrr 50 nc VR=20V,IF=50A,diF/dt=400A/µs 1) See Gate charge waveforms for parameter definition 2) Defined by design. Not subject to production test 6 Rev.2.2,

7 OptiMOS TM PowerMOSFET,40V 5Electricalcharacteristicsdiagrams Diagram1:Powerdissipation 160 Diagram2:Draincurrent Ptot[W] 80 ID[A] TC[ C] Ptot=f(TC) TC[ C] ID=f(TC);VGS 10V Diagram3:Safeoperatingarea 10 3 Diagram4:Max.transientthermalimpedance µs 1 µs 10 2 µs ms 0.5 ID[A] ms DC ZthJC[K/W] single pulse VDS[V] ID=f(VDS);TC=25 C;D=0;parameter:tp tp[s] ZthJC=f(tp);parameter:D=tp/T 7 Rev.2.2,

8 OptiMOS TM PowerMOSFET,40V Diagram5:Typ.outputcharacteristics ID[A] V 4.5 V 4 V 5 V 3.5 V 3.2 V 3 V 2.8 V Diagram6:Typ.drainsourceonresistance V 3.5 V 4 V 1.0 RDS(on)[mΩ] 10 V V 5 V 7 V 8 V VDS[V] ID=f(VDS);Tj=25 C;parameter:VGS ID[A] RDS(on)=f(ID);Tj=25 C;parameter:VGS Diagram7:Typ.transfercharacteristics 400 Diagram8:Typ.forwardtransconductance ID[A] gfs[s] C 25 C VGS[V] ID=f(VGS); VDS >2 ID RDS(on)max;parameter:Tj ID[A] gfs=f(id);tj=25 C 8 Rev.2.2,

9 OptiMOS TM PowerMOSFET,40V Diagram9:Drainsourceonstateresistance 2.00 Diagram10:Typ.gatethresholdvoltage RDS(on)[mΩ] max typ VGS(th)[V] Tj[ C] RDS(on)=f(Tj);ID=50A;VGS=10V Tj[ C] VGS(th)=f(Tj);VGS=VDS;ID=250µA Diagram11:Typ.capacitances 10 4 Ciss Coss Diagram12:Forwardcharacteristicsofreversediode C 150 C 25 C, max 150 C, max C[pF] Crss IF[A] VDS[V] C=f(VDS);VGS=0V;f=1MHz VSD[V] IF=f(VSD);parameter:Tj 9 Rev.2.2,

10 OptiMOSTM PowerMOSFET, 40 V Diagram 13: Avalanche characteristics Diagram 14: Typ. gate charge V 10 8V 25 C C 8 VGS [V] 125 C IAV [A] 32 V tav [µs] Qgate [nc] IAS=f(tAV); RGS=25 Ω; parameter: Tj(start) VGS=f(Qgate); ID=50 A pulsed; parameter: VDD Diagram 15: Drainsource breakdown voltage Gate charge waveforms VBR(DSS) [V] Tj [ C] VBR(DSS)=f(Tj); ID=1 ma 10 Rev. 2.2,

11 OptiMOSTM PowerMOSFET, 40 V 6 Package Outlines Figure 1 Outline TDSON8 FL, dimensions in mm/inches 11 Rev. 2.2,

12 OptiMOSTM PowerMOSFET, 40 V Figure 2 Outline Footprint TDSON8 FL 12 Rev. 2.2,

13 OptiMOSTM PowerMOSFET, 40 V Figure 3 Outline TDSON8 FL Tape 13 Rev. 2.2,

14 OptiMOSTM PowerMOSFET, 40 V Revision History Revision: , Rev. 2.2 Previous Revision Revision Date Subjects (major changes since last revision) Rev. 2.2 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: erratum@infineon.com Published by Infineon Technologies AG München, Germany 2014 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of noninfringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office ( Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. The Infineon Technologies component described in this Data Sheet may be used in lifesupport devices or systems and/or automotive, aviation and aerospace applications or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that lifesupport, automotive, aviation and aerospace device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. 14 Rev. 2.2,

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