14:332:231 DIGITAL LOGIC DESIGN

Transcription

1 :: IGIAL LOGI ESIGN Ivan Marsic, Rutgers University Electrical & omputer Engineering Fall Lecture #: Sequential Logic esign Practices ; ounters Sequential ircuit iming iagram Next-state Logic F State Memory Output Logic G output o function correctly, we must have: input excitation MAX t clk t ffpd(max) t comb(max) t setup > setup-time margin t ffpd(min) t comb(min) t hold > hold-time margin clock signal current state [ recall this diagram from Lecture # ] rosshatching indicates when change can happen: LOK t H t L t clock state of flip-flops t ffpd flip-flop outputs excitation logic t comb combinational outputs t ffpd t comb next state input needs t setup flip-flop inputs setup-time margin t setup t hold of

2 Sequential ircuit Functional iming We have to find the longest delays for each part ypical & longest delays are given for the circuit by the manufacturer For some latches & flip-flops, the timing parameters are in the book, able 8- on pages 8 8 e diagram shows only the functional behavior qualitative relationships, not actual delay quantities: LOK SYN_L SIG BUS AA AA don t care signal values Propagation, setup and hold times are not shown of Multibit Registers and Latches x -bit register Register = collection of flip-flops with a common clock input Note negative edge triggered flip-flops But the external has an inverter positive-edge triggered w.r.t. external input pin Asynchronous _L & _L buffered before fanning out x Wakerly, th Ed., Section 8.., page _L () () () () () () () () _L () () _L () () _L () () _L of

3 8-bit (octal) Register: x x Eight positive-edgetriggered flip-flops -state output buffer drives active-high output ommon active-low OE_L (output enable) input OE_L () () () () (8)!!! () () () () 8 8 x OE () () () (8) () () () () () 8 of 8-bit (octal) Register: x x Similar to x, but does not have -state output lock enable input _L x (8) () _L () () 8 of

4 Octal Latch x latches Output enable when is asserted and OE_L commands the three-state output (look up x above) 8 8 x OE 8 8 Register vs. latch, what s the difference? Register: edge-triggered behavior Latch: output follows input when is asserted of ounters ounter: Any sequential circuit for which the state diagram is a single cycle RESE S S S Sm S S A counter with m-states is called a modulo-m-counter, or sometimes a divide-by-m counter ounters can count up, count down, or count through other fixed sequences 8of

5 Ripple ounter flip-flops are used in simple counters he simplest solution is the ripple counter -bit binary ripple counter: It doesn t have! lock is connected to flip-flop clock input on the LSB bit flip-flop For all other bits, a flip-flop output is connected to the clock input circuit is not truly synchronous Output change is delayed more for each bit toward the MSB bit Resurgent because of low power consumption Synchronous counters are faster he operation of all flip-flops is synchronized by a common clock LSB MSB time = n t of [Recall Lecture #] (toggle) Flip-flop hanges state at every clock tick Signal on the output has frequency = ½ Used in counters and frequency dividers an be constructed from flip-flops flip-flop: N Next-state equation: = of

6 How Ripple ounter Works When there is a positive edge on the clock input of, complements (toggles) he clock input for flipflop is the complemented output of the first flip-flop, When flip changes from to, there is a positive edge on the clock input of causing to complement of Synchronous Serial ounter alled so b/c combined enable signals propagate serially from LSB to MSB Master count-enable N flip-flop toggles if-and-onlyif N= and all lowerorder counter bits are Fixed amount of logic per bit If period too short, the counter doesn t count Not enough time for a change in LSB to propagate to MSB N Serial enable logic LSB MSB of

7 Synchronous Serial ounter State table for binary counter: urrent State Next State Flip-Flop Inputs N toggles always (every clock tick) toggles every time = toggles every time and are both of Synchronous Parallel ounter Eliminates the problem w/ Synchronous Serial ounter Replace AN carry chain with ANs in parallel Each input driven w/ a dedicated AN gate just a single level of logic Advantages: Reduces path delays alled parallel gating Like carry lookahead he fastest binary counter N Parallel enable logic LSB MSB of

8 x MSI -bit ounter Most popular MSI counter Synchronous _L & L_L ( Load ) Synchronous parallel count enable P & acts also on RO ( ripple carry out ) Indicates a carry from MSB x L P A B A B RO _L Inputs L_L x x x x P x x x urrent State B A x x x x x x x x x x x x x x x x Next State B A B A B A B A of Logic iagram for x flip-flops, to have easier synchronous clear and load than flip-flop = pass data input (A,B,,) do counting function K K K K, P are to count on bits A to RO ( ripple carry out ), when is asserted of 8

9 Free-running ounter Operation Free-running == enable inputs enabled continuously ount if P and both asserted and Load if L_L is asserted [=] (overrides counting) lear if _L is asserted [=] (overrides loading and counting) All operations take place on rising edge RO is asserted if is asserted and count = LOK + V R x L P RPU A B A B RO U A B RO of Free-running -bit x ounter iming diagram for a free-running divide-by- counter is the MSB and A is the LSB From A on, each signal has ½ frequency of preceding one can be used as divide-by-, -, -8, or - counter 8 of

10 ecoding Binary-counter States A modulo-8 counter and decoder combined for a set of - out-of-m-coded signals, each representing a counter state Used for controlling a set of devices, based on counter state each output enables different device RPU +V LOK x L P A A B B RO U x8 but it has limitations due to a function hazard R G GA GB A B Y Y Y Y Y Y Y Y U S_L S_L S_L S_L S_L S_L S_L S_L of Modulo-8 ounter/ecoder iming iagram Glitches on state transitions in x8 (function hazard) he outputs of the counter do not change at exactly the same time Signal paths in the decoder x8 have different delays of

11 Glitch-free Outputs o achieve the same function of a mod-8 binary counter and decoder, but remove glitches on outputs: onnect decoder x8 outputs to a register (x) that samples the enable-decoded outputs on the next clock tick x is an 8-bit register with OE_L three-state output Registered outputs delayed by one clock tick Alternative solution: use an 8-bit ring counter LOK RPU x L P A B A B RO U +V R x8 G GA GB A B Y Y Y Y Y Y Y Y U x OE S_L RS_L S_L RS_L S_L RS_L S_L 8 RS_L S_L RS_L S_L RS_L S_L RS_L S_L RS8_L U of