# Latches and Flip-flops

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1 Latches and Flip-flops Latches and flip-flops are circuits with memory function. They are part of the computer's memory and processor s registers. SR latch is basically the computer memory cell Q=1 Q=0

2 SR latch with two NOR-gates If S = 1 and R = 0 it causes the upper gate to "0". The lower gate inputs then becomes 00 and it s output Q = 1. Since the upper gate now get "1" from both inputs, it now does not matter if S = 0. Q remains locked to output "1". If R = 1 and S = 0 it causes the lower gate to "0". Output is Q = 0. The upper gate inputs becomes 00 giving "1" at it s output and "1" at the input of the lower gate. Since the lower gate now get "1" from both inputs, it now does not matter if R = 0. Q remains unlocked to "0". Q=1 Q=0

3 Ex 9.1 Complete the timing diagram for the output signals Q and Q. The distance between the pulses is much longer than the gate delay. (Hint, what is the locking input signal for NOR gates?)

4 Ex 9.1 Complete the timing diagram for the output signals Q and Q. The distance between the pulses is much longer than the gate delay. (Hint, what is the locking input signal for NOR gates?)

5 Ex 9.1 Complete the timing diagram for the output signals Q and Q. The distance between the pulses is much longer than the gate delay. (Hint, what is the locking input signal for NOR gates?)

6 Ex 9.1 Complete the timing diagram for the output signals Q and Q. The distance between the pulses is much longer than the gate delay. (Hint, what is the locking input signal for NOR gates?)

7 Ex 9.1 Complete the timing diagram for the output signals Q and Q. The distance between the pulses is much longer than the gate delay. (Hint, what is the locking input signal for NOR gates?)

8 Ex 9.1 Complete the timing diagram for the output signals Q and Q. The distance between the pulses is much longer than the gate delay. (Hint, what is the locking input signal for NOR gates?)

9 Ex 9.1 Complete the timing diagram for the output signals Q and Q. The distance between the pulses is much longer than the gate delay. (Hint, what is the locking input signal for NOR gates?)

10 Ex 9.1 Complete the timing diagram for the output signals Q and Q. The distance between the pulses is much longer than the gate delay. (Hint, what is the locking input signal for NOR gates?)

11 Ex 9.1 Complete the timing diagram for the output signals Q and Q. The distance between the pulses is much longer than the gate delay. (Hint, what is the locking input signal for NOR gates?) For S = 1 and R = 1 the latch does not work, the outputs will then not be each others inverses, but both will be 0.

12 SR-latch characteristic table same forbidden A short "pulse" S = 1 "sets" the latch circuit and a short "pulse" R = 1 "resets" it. As long as the S = 0 and R = 0, the latch retains its value In the characteristic table the input combination S = 1 and R = 1 is forbidden!. For this combination would both gates outputs become "0" at the same time. For the other input combinations it applies that the outputs are each other's inverses. If you want to guarantee that the "other" output is always inverted, you have to "ban" the forbidden input signal combination.

13 Edge triggered Flip-flop In digital technology there is a distinction between simple latches and clocked flip-flops.? The limitation of the simple latch is that one can not enter a new value to the input while reading the output. The high speed of electronic circuits has made it necessary to develop more sophisticated circuits. Edge-triggered D flip-flop. D input is the data input, C input is the clock pulse input, hence the designation CP. The control input C has an edge trigger sign, a triangle. When the C input is reached by a positive edge, ie. the short period of time when C goes from "0" to "1", the D-input value is copied to the output Q. The output value is then locked until a new edge of the clock pulse is received.

14 Synchronization with D flip-flops D flip-flop used to synchronize the signal flow between the different parts of the computer. D flip-flops are used to stop the race between signals for the value to become stable. (Compare with the tollbooth that stops the cars).

15 Synchronization with D flip-flops D flip-flop used to synchronize the signal flow between the different parts of the computer. D flip-flops are used to stop the race between signals for the value to become stable. (Compare with the tollbooth that stops the cars).?

16 Synchronization with D flip-flops D flip-flop used to synchronize the signal flow between the different parts of the computer. D flip-flops are used to stop the race between signals for the value to become stable. (Compare with the tollbooth that stops the cars).?!

17 (9.4) Draw output Q in this timing diagram

18 (9.4) Draw output Q in this timing diagram

19 T-function Q T=0 Same T=1 Change, Toggle Q Sometimes this symbol of T-function is used. The T-flip-flop. Q Q

20 Ex 9.3 Draw the timing diagram for the output Q of the D flip-flop.

21 Ex 9.3 Draw the timing diagram for the output Q of the D flip-flop.

22 Ex 9.3 Draw the timing diagram for the output Q of the D flip-flop.

23 Ex 9.3 Draw the timing diagram for the output Q of the D flip-flop.

24 Ex 9.3 Draw the timing diagram for the output Q of the D flip-flop.

25 Ex 9.3 Draw the timing diagram for the output Q of the D flip-flop.

26 Ex 9.3 Draw the timing diagram for the output Q of the D flip-flop.

27 Ex 9.5 JK flip-flop was an older type of "universal flip-flop". Show how it can be used as the T-flip-flop and as D-flip-flop. Characteristic table same toggle

28 Ex 9.5 JK flip-flop can be used as the T flip-flop or D flip-flop. (When flip-flops are connected to each other there are usually the inverted outputs available, you will then not require the inverter to make the JK flip flop to D flip-flop.)

29 Ex 9.6 What is the maximum clock frequency that can be used to the circuit in the figure without the risk of failure? Suppose that t s = 20 ns t h = 5 ns t pd = 30 ns If the output is connected directly to input then must t < else one risking to - cut off the branch one is sitting on h t pd

30 t s = 20 ns t h = 5 ns t pd = 30 ns Ex 9.6

31 Ex 9.6 t s = 20 ns t h = 5 ns t pd = 30 ns T = t pd + t s f = 1 T = t pd 1 + t s = 1 ( ) [ ns] = 20 MHz

32

33 Asynchronous binary counter The figure above shows a binary counter with three flip-flops, the counting cycle has eight states so it is a modulo-8 counter. The counter is built of T-flip-flops, as they all have T = 1 they "toggles" at each clock pulse. The first flip-flop Q 0 "toggles" every clock pulse. The flip-flop Q 1 is clocked by the first flip-flop. It will therefore only "toggle" for every other clock pulse. The third flip-flop Q 2 will "toggle" for every other every other clock pulse. According to the binary table, the counter is counting in binary code. ( Q 2 Q 1 Q 0 : ).

34 Asynchronous counter weakness Asynchronous counter has the simplest possible structure. Since the clock pulses are routed through the flip-flops so they can not change state on exactly the same time. If you read the binary code on the outputs of flip-flops during the transition, then any code can appear for a short time! The flip-flops changes output one after another and you could say that the clock pulse "ripples" through the flip-flops (asynchronous counters are therefore sometimes called ripple counters). This problem has been solved with the synchronous counters.

35 BV 7.5 Given a 100-MHz clock signal, derive a circuit using T flip-flops to generate 50-MHz and 25-MHz clock signals. Draw a timing diagram for all three clock signals, assuming resonable delays.

36 BV 7.5 Given a 100-MHz clock signal, derive a circuit using T flip-flops to generate 50-MHz and 25-MHz clock signals. Draw a timing diagram for all three clock signals, assuming resonable delays.

37 BV 7.5 Given a 100-MHz clock signal, derive a circuit using T flip-flops to generate 50-MHz and 25-MHz clock signals. Draw a timing diagram for all three clock signals, assuming resonable delays. Output signals are delayed, after each stage!

38 Synchronous binary-counter The clock pulses go directly to all the flip-flops and therefore they change state at the same time. What flip-flop to turn on or not is controlled by T-inputs. The first flip-flop has T = 1, and it will toggle on every clock pulse. From the binary table, one can see that a certain flipflop should toggle is when all previous flip-flops outputs "1". toggle when all previous are 1 You get this condition from the AND gates in the so-called Carry-chain and they control the T-inputs. If you want to expand the counter it is done with one flip-flop and one AND gate per stage (bit). Up: Toggle if all previous are 1

39 Synchronous down-counter Carrychain toggle when all previous are 0 Down: Toggle if all previous are 0

40 BV 7.16 Design a three-bit up/down counter using T flip-flops. It should include a control input called UP/Down. If UP/Down = 0, then the circuit should behave as an up-counter. If UP/Down = 1, then the circuit should behave as a down counter.

41 BV 7.16 Up: Toggle if all previous are 1 Q 0 Q 1 Q 2 Down: Toggle if all previous are 0

42 BV 7.16 There is no requirement that the counter will be expanded with more bits. There is no requirement that the counter can be enabled. The circuit can be simplified : Q 0 Q 1 Q 2

43 BV 7.17 Repeat problem 7.16 using D flip-flops. T: Q0 Q 1 Q 2

44 BV 7.17 Repeat problem 7.16 using D flip-flops. T: Q0 Q 1 Q 2 Q Q

45 BV 7.17 Q Toggle T: Hold/Toggle Q D: Q0 Q1 Q2

46 In D Q Q 1 Q 2 Q 3 Q 4 D Q D Q D Q Out Clock Q Q Q Q A shift-register with a typical sequence. t 0 In 1 0 (a) Circuit Q 1 Q 2 Q 3 Q 4 = Out t t t t t t t (b) A sample sequence Figure A simple shift register.

47 BV 7.13 A universal shift register can shift in both the left-to-right and right-to-left directions, and it has parallell-load capability. Draw a circuit for such a shift register. Mode Universal shift register Right _ in Left _ in Parallell _ in Clock > Parallell _ out Right _ out Left _ out

48 BV 7.13 A universal shift register can shift in both the left-to-right and right-to-left directions, and it has parallell-load capability. Draw a circuit for such a shift register. This is a normal right shift shiftregister:

49 Mode = 2 Right shift

50 Mode = 1 Left Shift

51 Mode = 0 Parallell Load

52 Mode = 3 Hold

53 Multifunction shiftregister Mode 0 Parallell Load Mode 2 Right Shift Mode 1 Left Shift Mode 3 Hold

54 t su t h Clk D Q Figure 7.9. Setup and hold times.

55 BV 7.24 For the flip-flops in the counter in Figure 7.25, assume that t su = 3 ns, t h = 1ns and the propagation delay t pd is 1ns, and the gates and the 2-to-1 multiplexer has the propagation delay t pd equal to 1ns. What is the maximum clock frequency for which the circuit will operate correctly?

56 BV 7.24 Signal starts from flip-flop 0 after t pd and passes trough 3 ANDgates, 1 XOR-gate and 1 MUX on the way to flip-flop 3. There is also a demand on flip-flops that the D- signal shall have been stable t su before clock pulse. Check longest path! T min + 3 t = = 9 ns f = t 1 = T pd min = 9 1 AND [ ns] + t XOR + t = 111 MHz MUX + t SU =

57 BV 7.24 D-signal must also continnue to be stable during t h. t + h < t pd + t XOR tmux Check! Check shortest path!

58 ( Ex. 9.7 ) The figure shows three different state machines. Specify the state machine (A, B or C) that can operate at the highest clock speed. Highlight the critical path (the path that limits clock frequency) in this figure and calculate the period time for the clock signal Clk.

59 ( Ex. 9.7 )

60 Heuristic methods of construction? This time, we have constructed counters and shift registers by being "clever". (Heuristic methods of construction - based on experience) It's not every day one is so slick, so the next exercise is about the systematic design methods that are general and therefore can be used on any sequence circuit problem, and at all days. The Moore machine and the Mealy machine.

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