Lecture 13: Sequential Networks Flip flops and Finite State Machines
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1 Lecture 13: Sequential Networks Flip flops and Finite State Machines CSE 140: Components and Design Techniques for Digital Systems Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego 1
2 T T Flip-Flop (Toggle) State table PS T (t+1) Characteristic Expression (t+1) = (t)t(t) + (t)t (t) 2
3 Using a JK F-F to implement a D and T F-F x J K iclicker The above circuit behaves as which of the following flip flops? A. D F-F B. T F-F C. None of the above 3
4 Using a JK F-F to implement a T F-F T J K T flip flop 4
5 5
6 6
7 7
8 8
9 Flip flops Write the state-table of the following flip-flops D JK T 9
10 Sequential Networks Y A B C D Combinational X S(t) RTL: Register-Transfer Level Description 1. Components F-Fs 2. Specification 3. Implementation: Excitation Table 10
11 Specification Combinational Logic Truth Table Boolean Expression Logic Diagram (No feedback loops) Sequential Networks: State Diagram (Memory) State Table and Excitation Table Characteristic Expression Logic Diagram (FFs and feedback loops) 11
12 What we will learn: 1. Describe the desired behavior of a sequential circuit over time (FSMs) 2. Given the behavior of a sequential circuit, implement the circuit Wall-E is a Finite State Machine Describing Wall-E Active Inactive Implementing Wall-E 12
13 Finite State Machines: Describing circuit behavior over time Symbol/ Circuit 2 bit Counter 13
14 Finite State Machines: Describing circuit behavior over time Output over time Symbol/ Circuit Free running 2 bit Counter time 1 0 What is the expected output of the counter over time? 14
15 Finite State Machines: Describing circuit behavior over time Symbol/ Circuit Diagram that depicts behavior over time 2 bit Counter
16 State: What is it? Why do we need it? Symbol/ Circuit Behavior over time 2 bit Counter t 1 t 2 time PI : At time t 1, what information is needed to produce the output of the counter at the next rising edge of the clock (i.e t 2 )? A. All the outputs of the counter until t 1 B. The initial output of the counter at time t=0 C. The output of the counter at current time t 1 D. We cannot determine the output of the counter at t 2 prior to t 2 16
17 Implementing the 2 bit counter S 0 Current state Next State S 0 S 1 S 3 S 1 S 1 S 2 S 2 S 3 S 3 S 0 S 2 State Diagram 1 (t) 0 (t) 1 (t+1) 0 (t+1) State Table 17
18 State Table 1 (t) 0 (t) 1 (t+1) 0 (t+1) PI : Which of the following is the likely structure of the circuit realization of the counter A. Combinational circuit B. 0 (t) Combinational circuit 1 (t) D D C. Circuit with no flip flops 0 (t) Combinational circuit D 1 (t) Circuit with 2 flip flops Circuit with one flip flop 18
19 State Table 1 (t) 0 (t) 1 (t+1) 0 (t+1) D 0 (t) = 0 (t) D 1 (t) = 0 (t) 1 (t) + 0 (t) 1 (t) B. 0 (t) Combinational 1 (t) circuit D D Circuit with 2 flip flops 19
20 1 (t) 0 (t) 1 (t+1) 0 (t+1) State Table 0 (t+1) = 0 (t) 1 (t+1) = 0 (t) 1 (t) + 0 (t) 1 (t) 0 (t) 1 (t) D D We store the current state using D-flip flops so that: Inputs to the combinational circuit don t change while the next output is being computed The transition to the next state only occurs at the rising edge of the clock Implementation of 2-bit counter 20
21 Generalized Model of Sequential Circuits Y X S(t) 21
22 Let s implement our free running 2-bit counter using T-flip flops 0 (t) Combinational circuit 1 (t) T T Circuit with 2 T-flip flops Excitation table id 1 (t) 0 (t) T 1 (t) T 0 (t) 1 (t+1) 0 (t+1)
23 Let s implement our free running 2-bit counter using T-flip flops 0 (t) 1 (t) T T Circuit with 2 T-flip flops Excitation table id 1 (t) 0 (t) T 1 (t) T 0 (t) 1 (t+1) 0 (t+1)
24 Let s implement our free running 2-bit counter using T-flip flops 0 (t) 1 (t) T T T 0 (t) = T 1 (t) = Circuit with 2 T-flip flops Excitation table id 1 (t) 0 (t) T 1 (t) T 0 (t) 1 (t+1) 0 (t+1)
25 Free running counter with T flip flops 1 T 0 T 1 T 1 T 0 (t) = 1 T 1 (t) = 0 (t) 25
26 Let s implement our free running 2-bit counter using JK-flip flops 0 (t) Combinational circuit 1 (t) Circuit with 2 JK-flip flops Excitation table id 1 (t) 0 (t) J 1 (t) K 1 (t) J 0 (t) K 0 (t) 1 (t+1) 0 (t+1)
27 Let s implement our free running 2-bit counter using JK-flip flops 0 (t) Combinational circuit 1 (t) Circuit with 2 JK-flip flops Excitation table id 1 (t) 0 (t) J 1 (t) K 1 (t) J 0 (t) K 0 (t) 1 (t+1) 0 (t+1) X X X X
28 Let s implement our free running 2-bit counter using JK-flip flops 0 (t) Combinational circuit 1 (t) Circuit with 2 JK-flip flops Excitation table id 1 (t) 0 (t) J 1 (t) K 1 (t) J 0 (t) K 0 (t) 1 (t+1) 0 (t+1) X 1 X X X X 0 1 X X 1 X
29 Let s implement our free running 2-bit counter using JK-flip flops 0 (t) Combinational circuit 1 (t) J 1 (t) = 0 (t) K 1 (t) = 0 (t) J 0 (t) = 1 K 0 (t) =1 Circuit with 2 JK-flip flops Excitation table id 1 (t) 0 (t) J 1 (t) K 1 (t) J 0 (t) K 0 (t) 1 (t+1) 0 (t+1) X 1 X X X X 0 1 X X 1 X
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