2 n. (finite state machines).

Transcription

1 . - S,, T FI-FO. ;. 2. ;,,.,, (sequential).. ( ) ; (state) (state variables),.,, (state)..,,..,,. 4. ;. n 2 n., 2 n,, (finite state machines). 5. (feedback).,..,.,,. 6.,,., ( )..

2 ,.,. 7., ( ).,.., AN,., AN. 2. _ _ t T=t per t t per t per t f=/t t IG uty ycle = t /t OW uty ycle = t /t 2.., IG IG, OW. quartz. 3. T VF VF2 2p M U2 SN744 U 49S_Y2BS (feedback sequential circuit),, (latch) (flipflops),. 9. k 2 2p 4 Mz. VF VF2. 2.5u 5.u 7.5u.u U M 2

3 3 : : : : T. 2.5u 5.u 7.5u.u 4. Mz.... (clocked synchronous state machine) Flip- Flops,. 2. (latch),. 3. Flip-Flops flip-flop., flip-flops. bit. flip-flops bit. flip-flop flip-flop. flip-flop ( ),. flip-flop. 4. S T5. S ' S :2 S: U U2 :3 ':4. 5.n.u.5u 2.u 5. S NO. 5 S NO. S- -.

4 .. / S. S + + ( ) ( ). / S. S=,=, =, =..,.. =, =. =, =.,. S. S :2 S: U U2 :3 ':4 6. S NAN. T S '. 5.n.u.5u 2.u 7. S. flip-flop.. S. 6 S- NAN 7. / ( 2). S= =. S,. S ( ) ( ) 2. S NAN.. S-FF ( 8) 4bits ( 9). 4 :2 U3 U : S: U2 ':4 8.

5 5 T S '..u 2.u 3.u 4.u 5.u S = S Flip-Flop S S. M. To S flip-flop. ( ).. 5k :3 : M U3 SN74 U SN74 :4 T S '. 2.5u 5.u 7.5u.u 6. S flip-flop. S-FF 4bit 2. 3 S ( Flip-Flops). ata 7. S-Flip-Flop NAN. ata S (set) (reset) S (set) (reset) 3 4 SFF S 2 ' S 25k S:2 U4 SN74 U2 SN74 ':5. 8. S-Flip-Flop. Flip-Flop S. = :.. + =. S=, =, = :. + =X. S=, =, = :. + =. S=, =, = :. + =. S=, =, = :. + =X. ( ) flip-flop S ( Flip-Flop ).. S-FF. S-FF TINA NAN ( 4) ( 5). U5 k U7 4k U8 2k S:2 : :3 U3 SN74 U4 SN74 U SN74 U2 SN74 U6 S :4 ':5 2:6

6 9.. T S ' 2..m 2.m 3.m.. 2. ( 3) ( 6) S-FF. 3. S-FF. S + X X 3. ( 7) ( 8). a) ( ). b) ; U T S M :3 S:2 U2 Noname :4 S :. 2.5u 5.u 7.5u.u FI-FO. arnaugh S-FF. arnaugh, : + = S + S = ( S flip-flop S=, S=,=.) S flip-flop S. -flip-flop. :,. =. =, = = : A =, = = : -flip-flop (ata).. arnaugh -FF. +

7 7 Flop. 4. -Flip , - FF 23,. T k Flop. 9. -Flip- -FF : + =. FF. -FF TINA NAN. ( 2, 2). u :2 : M 5 SN74 3 SN74 4 SN74 U2 5 SN74 2 SN74 :3 2. -Flip-Flop, NAN o -Flip-Flop TINA. T U4 5 U SN7474 2:4. 2.u 4.u 6.u FF -atch. ( 24, 25). u u M :2 : M k E 24. U SN74 U3 SN74 E U2 5 U4 5 U SN7474 :3 2:4 2..u 2.u 3.u 4.u 5.u 6.u 7.u

8 8 T u 5.u 7.5u.u 7. -FI-FO 25. To -flip-flop S-flip-flop S,.,, S.,.,, (t+)=,, reset (t+)=,, set (t+)=,, toggle ( ) (t+)= 27. -FF. : (t+)= +. -flip-flop, =,...., flip-flop.,,. flip-flop, -. T-flip-flop. ata 5. -FF (reset) S (set) 2 '. ( ) -FF SN7476. ; FF FF.

9 9 8. T-FI-FO -FF flip-flop (toggle),. flip-flop, =. =, (t+)=,. T + 6. T-FF. 3 (reset) FF - (master-slave) FF. FF - FF, (master), (slave). FF -. S FF FF. 3 S-FF. S k 4k S:2 : S 4 S (set) 2 ' S U3 U master:4 2k :3 U8 U5 slave: FF -FF. 4. T-FF. Master U4 S U Slave U2 U9 U7 'slave:8 'master:5 U6 2master:6 U2 2slave:9 S S U Master U3 Slave 3. S-FF. -FF : + = T + T 9. FI-FOS - FF. ( - ), -. FF, (edge triggering). 32. master slave. T S master 'master 2master slave 'slave 2slave..m 2.m 3.m 32. S-FF.

10 FF -,,. - FF FF S. 33 -FF. FF. u M u U3 5 U U FF M, S M. T M S : :2 :3 M: FF -. FF -. FF U2 S:5..u 2.u 3.u 4.u 5.u 6.u 7.u ( ).,, FF.,, -., FF, FF. FF. FF, FF. ( arnaugh); ( -FF). reset lear 7476 ; ; 2., - FF T-FF. 3. -FF -FF. 4. -FF ( 35) ( 36). u M k U SN74 E 35.

11 T k. 2.u 4.u 6.u FF -FF. 6. -FF ( 37) ( 38). 7. T-FF ( 39) ( 4). T ' T u M 39. U 5 U2 SN74S3 ' r 5. 2.u 4.u 6.u U9 T k ' U7 M k 38. U SN7476 r 5 ' u.u 5.u 2.u SN742 - UA NEGATIVE EGE- TIGGEE FI-FO WIT ESET AN EA. encil Box (MOE SEET TUT TABE) SN742 ( 4). ( 42).

12 2. SN742 -FF. encil Box SN742 -FF. (SN744). ( 44).. 4. SN742 - UA NEGATIVE EGE-TIGGEE FI-FO WIT ESET AN EA.. 6,7 6 V 5 () 8 6 5,9 () 3,,3 2,2 5,4 () 4, 4, (S) U SN74S2 5,9 6,7 3, 2,2,3 6,7 6 V 5 () 8,inv(7) 6,inv(4) 5,9 () 3,,3 2,2 5,4 5,4 () 4, , (S) U SN74S2 5,9 6,7 5, SN742 -FF. encil Box SN742 -FF. ( 43). N() = No Internal onnection. () () = = 2 3 6,7 5,9 () (S) = 3, = 6 inv () inv(2) 2,2 inv SN744,3 V ,(2,2),3 5,4 4, 4, 3,(2,2) U SN74S2 5,9 6,7,3 5, SN7472 AN-GATE MASTE-SAVE NEGATIVE EGE-TIGGEE FI-FO

13 3 WIT ESET AN EA.. SN7472 AN-GATE MASTE- SAVE NEGATIVE EGE-TIGGEE FI-FO WIT ESET AN EA. encil Box SN7472. ( 45). ( : 7472 and. V. preset clear. ). ( 46).. V () 8 () AN AN E 5 SN SN747 AN-GATE MASTE-SAVE OSITIVE EGE-TIGGEE FI-FO WIT ESET AN EA. 2. SN747 AN-GATE MASTE- SAVE OSITIVE EGE-TIGGEE FI-FO WIT ESET AN EA. encil Box SN747. ( 47). ( 48).. () () E V not not AN not AN SN N() = No Internal onnection FF -FF, MUX 4x NOT = 2 - = 2 U6 U5 U4 SN744 U9 MyMux4x I I MyMux4x I2 I3 S :3 S F 2 U2 5 U3 5 U SN7474 :4 5 :2 : 49. -FF -FF, MUX 4x NOT.

14 T FF, x, y S. -FF ( 5) m 5.m 75.m.m x:3 y:4 y u y u x y x y x y U7 FA A B in U SN7474 :2 U : Sum x y out = x y + x + y. FF : = out = x y + x + y. : (t+) = = out = x y + x + y x y (t+) S U3 5 FA out Sum : S:5 M ( State Editor ). 53. State Editor, V ( ). T x y S u 4.u 6.u 8.u 53.. library IEEE; use IEEE.std_logic_64.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity SAME is port ( reset: in std_logic; : in std_logic; x: in std_logic; y: in std_logic; S: out std_logic; : out std_logic); end; architecture SAME_arch of SAME is type SMachine_type is (S,S); signal SMachine: SMachine_type := S; begin SMachine_machine: process () begin if reset = '' then S<=''; <=''; SMachine <= S; elsif 'event and = '' then case SMachine is when S => <= ''; if x='' and y='' then S<=''; SMachine <= S; elsif x='' and y=''then S<=''; SMachine <= S; elsif x='' and y=''then S<=''; SMachine <= S;

15 5 elsif x='' and y=''then S <= ''; SMachine <= S; when S => <='' if x='' and y='' then S<=''; SMachine <= S; elsif x='' and y=''then S<=''; SMachine <= S; elsif x='' and y=''then S<=''; SMachine <= S; when others => null; end case; end process; end SAME_arch;. V. 5. -FF x. FF: A = x, A = B', B = x, B = A. A(t+) B(t+).. -FF : (t+) = ' + '. FF : A(t+) = x A' + B A B(t+) = x B' + A' B. O ( 8). 54 ( State Editor ). V FF A B x A + B + A A B B library IEEE; use IEEE.std_logic_64.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity SAME is port ( reset: in std_logic; : in std_logic; x: in std_logic; A: out std_logic; B: out std_logic); end; architecture SAME_arch of SAME is type SMachine_type is (S,S3,S2,S); signal SMachine: SMachine_type := S; begin SMachine_machine: process () begin if reset='' then A<=''; B<=''; SMachine <= S; elsif 'event and = '' then case SMachine is when S => A<=''; B<=''; if x='' then SMachine <= S3; elsif x=''then SMachine <= S; when S3 => A<=''; B<=''; if x='' or x='' then SMachine <= S2; when S2 => A<=''; B<=''; if x='' then SMachine <= S; elsif x=''then SMachine <= S; when S => A<=''; B<=''; if x='' then SMachine <= S; elsif x=''then SMachine <= S3; when others => null; end case; end process; end SAME_arch;

16 2. V. 6. ( 9). (.. =,.. = ).. b, e. e ( ) b., d h. h ( ) d ( )..... X= X= X= X= a f b b d c c f e d g a e d c f f b g g h h g a X= X= X= X= a f b b d c c f e d g a e d c f f b g g h h g a.. a c, c ( ) a X= X= X= X= a f b b d c c f b d g a f f b g g d..... X= X= X= X= a f b b d a d g a f f b g g d a, :... : state a f b c e d g h g g h a input output 3. : state a f b a b d g d g g d a input output 4..

17 7 8. -FF x. x=. x=.., 55. ( 5) A B x A B 5. -FF : (t+) =. : A(t+) = A (A,B,X) = (3,4,6,7) B(t+) = B (A,B,X) = (,2,3,6). arnaugh : A = BX + AX' B = A'X + BX' 56. O V FSM Editor 3. x' A x B x A' x' B x x,k U2 U6 U7 U8 U9 x' : A = BX + AX' 56. library IEEE; use IEEE.std_logic_64.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; x U U x:2 entity SAME is port ( reset: in std_logic; : in std_logic; x: in std_logic; a: out std_logic; b: out std_logic); end; architecture SAME_arch of SAME is type SMachine_type is (S,S,S3,S2); signal SMachine: SMachine_type := S; begin SMachine_machine: process () begin if reset='' then a<=''; b<=''; SMachine <= S; elsif 'event and = '' then case SMachine is when S => a<=''; b<=''; if x='' then SMachine <= S; elsif x=''then SMachine <= S; when S => a<=''; b<=''; if x='' then SMachine <= S3; elsif x=''then SMachine <= S; A B A B = A'X + BX' B U3 U4 U5 U U2 A A' B B' A:3 B:4

18 when S3 => a<=''; b<=''; if x='' then SMachine <= S3; elsif x=''then SMachine <= S2; when S2 => a<=''; b<=''; if x='' then SMachine <= S2; elsif x=''then SMachine <= S; when others => null; end case; end process; end SAME_arch; 3. V State Editor. 9. -FFs x. An E= x. = x=. = x=. X X X X X X X X X X X X X X X X X X X X X X 6. 8 FFs. A A A = BEX +B'EX' = E (B X)'. FSM Editor 57. A = BEX +B'EX' = E (B X)' FI-... FOS A B E X A B A A B B X X X X X X X X X X B B = E

19 9 end; x: in std_logic; E: in std_logic; A: out std_logic; B: out std_logic); architecture SAME_arch of SAME is type SMachine_type is (S,S,S2,S3); signal SMachine: SMachine_type := S; begin B B = E 58. 2bit X=, =, V. T E x A B x u E u U6 5 k x:3 B E count-up : U SN7486 U2 SN744 E:2 E U3 SN748 A SN7476 A:4 B SN7476 B:5. 2.5m 5.m 7.5m.m count-down B SMachine_machine: process () begin if reset='' then A<=''; B<=''; SMachine <= S; elsif 'event and = '' then case SMachine is when S => A<=''; B<=''; if E='' and x='' then SMachine <= S3; elsif E='' and x=''then SMachine <= S; elsif (E='' and x='') or (E='' amd x='')then SMachine <= S; when S => A<=''; B<=''; if E='' and x='' then SMachine <= S; elsif E='' and x=''then SMachine <= S2; elsif (E='' and x='') or (E='' and x='')then SMachine <= S; when S2 => A<=''; B<=''; if E='' and x='' then SMachine <= S; elsif E='' and x=''then SMachine <= S3; elsif (E='' and x='') or (E='' and x='')then SMachine <= S2; when S3 => A<=''; B<=''; if E='' and x='' then SMachine <= S2; elsif E='' and x=''then SMachine <= S; elsif (E='' and x='') or (E='' and x='')then SMachine <= S3; when others => null; end case; end process; end SAME_arch; 4. V State Editor. library IEEE; use IEEE.std_logic_64.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity SAME is port ( reset: in std_logic; : in std_logic;

20 2. a).,.5 Mz. b) 3 s. c).mz.. lock2 Sources Voltage in Meters. 6. Analysis igital Timing Analysis 3 s (3u ), 6. k 2 5k 3 M U4 U5 5 x y z w x y z w y z' y z x y z U SN744 x' U SN744 y' U7 SN744 z' U6 SN7432 y+z' U8 SN748 yz y y+z' w x' yz y' U FFs ( 63). A B G 2 3 2G Y 2Y k : U2 SN7474 U3 SN7474 :3 2:2 2 T 6. ==> ( ) ==> ( ) u 2.u 3.u 6.

21 2 V GUAE BO IBAY ieee; USE ieee.std_logic_64.all; ENTITY latch IS OT (d, clk: IN ST_OGI; q: OUT ST_OGI); EN latch; AITETUE latch OF latch IS b: BO (clk='') guard expression q <= GUAE d; -- guarded statement EN BO b; EN latch; FF GUAE BO IBAY ieee; USE ieee.std_logic_64.all; ENTITY dff IS OT ( d, clk, rst: IN ST_OGI; q: OUT ST_OGI); EN dff; AITETUE dff OF dff IS b: BO (clk'event AN clk='') q <= GUAE '' WEN rst='' ESE d; EN BO b; EN dff; V. OESS, FUNTION OEUE ( ).,..,,. (behavioral code)., OESS, FUNTIO OEUE). IF, WAIT, ASE OO. VAIABES ( OESS, FUNTIO OEUE)., SIGNA, VAIABE,. OESSES. FUNTIONS OEUES. OESS OESS V. IF, WAIT, ASE, OO ( WAIT). OESS, ( WAIT ). : [label:] OESS (sensitivity list) [VAIABE name type [range] [:= initial_value;]] (sequential code) EN OESS [label]; VAIABES.,.. label.. V., (.. ). EVENT... clk, clk EVENT TUE clk

22 ( ).. FF eset IBAY ieee; USE ieee.std_logic_64.all; ENTITY dff IS OT (d, clk, rst: IN ST_OGI; q: OUT ST_OGI); EN dff; AITETUE behavior OF dff IS OESS (clk, rst) IF (rst='') TEN q <= ''; ESIF (clk'event AN clk='') TEN q <= d; EN OESS; EN behavior; V - : SIGNA VAIABE. SIGNA AAGE, ENTITY AITETUE,, VAIABE (.. OESS)., SIGNA, VAIABE. VAIABE, OESS., SIGNA. VAIABE,. SIGNA ( OESS), OESS. SIGNA «<=» VAIABE = «:=». IF IF, WAIT, ASE OO. 22 OESS, FUNTION OEUE. IF.,, ( IF/ESE ),. IF : IF conditions TEN assignments; ESIF conditions TEN assignments;... ESE assignments; : IF (x<y) TEN temp:=""; ESIF (x=y AN w='') TEN temp:=""; ESE temp:=(otes =>''); WAIT WAIT IF., WAIT. IF, ASE OO, OESS WAIT. WAIT : WAIT UNTI signal_condition; WAIT ON signal [, signal2,... ]; WAIT FO time; WAIT UNTI,,. OESS, WAIT UNTI OESS. OESS. : 8bit reset: OESS -- no sensitivity list WAIT UNTI (clk'event AN clk=''); IF (rst='') TEN output <= ""; ESIF (clk'event AN clk='') TEN output <= input; EN OESS; WAIT ON,. OESS., OESS

23 23 rst clk. : 8bit reset: OESS WAIT ON clk, rst; IF (rst='') TEN output <= ""; ESIF (clk'event AN clk='') TEN output <= input; EN OESS;, WAIT FO ( testbenches)...: WAIT FO 5ns;. FF eset WAIT ON IF IBAY ieee; USE ieee.std_logic_64.all; ENTITY dff IS OT (d, clk, rst: IN ST_OGI; q: OUT ST_OGI); EN dff; AITETUE dff OF dff IS OESS WAIT ON rst, clk; IF (rst='') TEN q <= ''; ESIF (clk'event AN clk='') TEN q <= d; EN OESS; EN dff; ASE ASE,, ( IF, WAIT OO). : ASE identifier IS WEN value => assignments; WEN value => assignments;... EN ASE; : ASE control IS WEN "" => x<=a; y<=b; WEN "" => x<=b; y<=c; WEN OTES => x<=""; y<="zzzz"; EN ASE; ASE ( ) WEN ( ).,, OTES. NU ( UNAFFETE),... : WEN OTES => NU;., ASE ( ), WEN. WEN, «WEN value» : WEN value -- single value WEN value to value2 -- range, for enumerated data types -- only WEN value value value or value2 or.... FF reset ASE IBAY ieee; -- Unnecessary declaration, because -- BIT was used instead of ST_OGI USE ieee.std_logic_64.all; ENTITY dff IS OT (d, clk, rst: IN BIT; q: OUT BIT); EN dff; AITETUE dff3 OF dff IS OESS (clk, rst) ASE rst IS WEN '' => q<=''; WEN '' => IF (clk'event AN clk='') TEN q <= d; WEN OTES => NU; -- Unnecessary, rst is of type BIT EN ASE; EN OESS; EN dff3;

24 OO OO. IF, WAIT, ASE, OO OESS, FUNTION OEUE. OO : FO / OO:. [label:] FO identifier IN range OO (sequential statements) EN OO [label]; WIE / OO:. [label:] WIE condition OO (sequential statements) EN OO [label]; EXIT:. [label:] EXIT [label] [WEN condition]; NEXT: Used for skipping loop steps. [label:] NEXT [loop_label] [WEN condition];.. OO/EXIT. EXIT escape ( OO, )., OO. IBAY ieee; USE ieee.std_logic_64.all; ENTITY eadingzeros IS OT ( data: IN ST_OGI_VETO (7 OWNTO ); zeros: OUT INTEGE ANGE TO 8); EN eadingzeros; AITETUE behavior OF eadingzeros IS OESS (data) VAIABE count: INTEGE ANGE TO 8; count := ; FO i IN data'ange OO ASE data(i) IS WEN '' => count := count + ; WEN OTES => EXIT; EN ASE; EN OO; zeros <= count; EN OESS; EN behavior; ASE IF 24, ESE IF/ESE ( ASE),., IF ( ),.,, V IF ASE., : ---- With IF: IF (sel="") TEN x<=a; ESIF (sel="") TEN x<=b; ESIF (sel="") TEN x<=c; ESE x<=d; ---- With ASE: ASE sel IS WEN "" => x<=a; WEN "" => x<=b; WEN "" => x<=c; WEN OTES => x<=d; EN ASE; ASE WEN ASE WEN., WEN ASE. : WEN ASE OESS, FUNTION OESS, FUNTION OEUE OEUE, WIT /

25 25 SEET / WEN UNAFFETE NU, : ---- With WEN: WIT sel SEET x <= a WEN "", b WEN "", c WEN "", UNAFFETE WEN OTES; ---- With ASE: ASE sel IS WEN "" => x<=a; WEN "" => x<=b; WEN "" => x<=c; WEN OTES => NU; EN ASE; V - : SIGNA VAIABE. ONSTANT GENEI. ONSTANT SIGNA ( ).. VAIABE ( OESS, FUNTION OEUE). SIGNA VAIABE. ONSTANT ONSTANT : ONSTANT name : type := value; : ONSTANT set_bit : BIT := ''; ONSTANT datamemory : memory := (('','','',''), ('','','',''), ('','','','')); ONSTANT AAGE, AITETUE.,,. ENTITY ( OT) ENTITY., AITETUE ( ) AITETUE., ONSTANT AITETUE AAGE. SIGNA SIGNA,.... OTS ENTITY SINGA. : SIGNA name : type [range] [:= initial_value]; : SIGNA control: BIT := ''; SIGNA count: INTEGE ANGE TO ; SIGNA y: ST_OGI_VETO (7 OWNTO ); SIGNA ONSTANT. SIGNA (.. OESS)., OESS, FUNTION OEUE. SIGNA «<=».,. SIGNA., (.. ).,, VAIABE..

26 ..,.,, OEUE,. VAIABE SIGNA. IBAY ieee; USE ieee.std_logic_64.all; ENTITY count_ones IS OT ( din: IN ST_OGI_VETO (7 OWNTO ); ones: OUT INTEGE ANGE TO 8); EN count_ones; AITETUE not_ok OF count_ones IS SIGNA temp: INTEGE ANGE TO 8; OESS (din) temp <= ; -- not immediate FO i IN TO 7 OO IF (din(i)='') TEN temp <= temp + ; -- not immmediate EN OO; ones <= temp; EN OESS; EN not_ok; temp, ones., ones OUT BUFFE, ones. ones (OUT), (temp). VAIABE ONSTANT SIGNA, VAIABE. OESS, FUNTION, OEUE ( ),.,,. VAIABE, : VAIABE name : type [range] [:= init_value]; 26 : VAIABE control: BIT := ''; VAIABE count: INTEGE ANGE TO ; VAIABE y: ST_OGI_VETO (7 OWNTO ) := ""; VAIABE, OESS, FUNTION OEUE. VAIABE «:=»., SIGNA,,.., VAIABE SIGNA. VAIABE, VAIABE. IBAY ieee; USE ieee.std_logic_64.all; ENTITY count_ones IS OT ( din: IN ST_OGI_VETO (7 OWNTO ); ones: OUT INTEGE ANGE TO 8); EN count_ones; AITETUE ok OF count_ones IS OESS (din) VAIABE temp: INTEGE ANGE TO 8; temp := ; FO i IN TO 7 OO IF (din(i)='') TEN temp := temp + ; EN OO; ones <= temp; EN OESS; EN ok; SIGNA VAIABE SIGNA VAIABE <= :=

27 27. ( OESS, FUNTION, OEUE). AAGE, ENTITY, AITETUE. ENTITY OTS SIGNA. ( OESS, FUNTION, OEUE). ( ). ( OESS, FUNTION OEUE)... : IF (s='') TEN sel <= sel + 2; ASE sel IS WEN => y<=a; WEN => y<=b; WEN 2 => y<=c; WEN 3 => y<=d; EN ASE; EN OESS; EN not_ok; SIGNA., sel<=sel+, sel<=, sel. sel<=sel+2. VAIABE,. SIGNA ( sel). OESS. sel<=sel+2., VAIABE. VAIABE: -- Solution 2: using a VAIABE (ok) IBAY ieee; USE ieee.std_logic_64.all; ENTITY mux IS OT ( a, b, c, d, s, s: IN ST_OGI; y: OUT ST_OGI); EN mux; SINGA ( ): -- Solution : -- using a SIGNA (not ok) -- IBAY ieee; USE ieee.std_logic_64.all; ENTITY mux IS OT ( a, b, c, d, s, s: IN ST_OGI; y: OUT ST_OGI); EN mux; AITETUE not_ok OF mux IS SIGNA sel : INTEGE ANGE TO 3; OESS (a, b, c, d, s, s) sel <= ; IF (s='') TEN sel <= sel + ; AITETUE ok OF mux IS OESS (a, b, c, d, s, s) VAIABE sel : INTEGE ANGE TO 3; sel := ; IF (s='') TEN sel := sel + ; IF (s='') TEN sel := sel + 2; ASE sel IS WEN => y<=a; WEN => y<=b; WEN 2 => y<=c; WEN 3 => y<=d; EN ASE; EN OESS; EN ok;

28 FF SIGNA FF: IF (clk'event AN clk='') TEN q <= d; EN OESS; qbar<= NOT q; EN ok; 28 OT SIGNA. q<=d qbar<=not q, OESS. qbar, q. qbar q. qbar, Solution : not O IBAY ieee; USE ieee.std_logic_64.all; ENTITY dff IS OT ( d, clk: IN ST_OGI; q: BUFFE ST_OGI; qbar: OUT ST_OGI); EN dff; AITETUE not_ok OF dff IS OESS (clk) IF (clk'event AN clk='') TEN q <= d; qbar <= NOT q; EN OESS; EN not_ok; qbar <= NOT q, OESS, Solution 2: O IBAY ieee; USE ieee.std_logic_64.all; ENTITY dff IS OT ( d, clk: IN ST_OGI; q: BUFFE ST_OGI; qbar: OUT ST_OGI); EN dff; AITETUE ok OF dff IS OESS (clk) 6: count SIGNA count2 VAIABE. : IBAY ieee; USE ieee.std_logic_64.all; ENTITY freq_divider IS OT ( clk : IN ST_OGI; out, out2 : BUFFE ST_OGI); EN freq_divider; AITETUE example OF freq_divider IS SIGNA count : INTEGE ANGE TO 7; OESS (clk) VAIABE count2 : INTEGE ANGE TO 7; IF (clk'event AN clk='') TEN count <= count + ; count2 := count2 + ; IF (count =? ) TEN out <= NOT out; count <= ; IF (count2 =? ) TEN out2 <= NOT out2; count2 := ; EN OESS; EN example; flip-flops.

29 29,. SIGNA flip-flop.., OESS, FUNTION OEUE ( IF signal EVENT WAIT UNTI VAIABE, flip-flops OESS ( FUNTION OEUE). VAIABE, ( ), flip-flops. VAIABE.,, output output2 ( flip-flops), (clk): OESS (clk) IF (clk'event AN clk='') TEN output <= temp; -- output stored output2 <= a; -- output2 stored EN OESS;, output ( output2 ): OESS (clk) IF (clk'event AN clk='') TEN output <= temp; -- output stored output2 <= a; -- output2 not stored EN OESS;, temp x ( ): OESS (clk) VAIABE temp: BIT; IF (clk'event AN clk='') TEN temp <= a; x <= temp; -- temp causes x to be stored EN OESS; FF FF FF: SIGNA, FFs: -- Solution : Two FFs IBAY ieee; USE ieee.std_logic_64.all; ENTITY dff IS OT ( d, clk: IN ST_OGI; q: BUFFE ST_OGI; qbar: OUT ST_OGI); EN dff; AITETUE two_dff OF dff IS OESS (clk) IF (clk'event AN clk='') TEN q <= d; -- generates a register qbar <= NOT d; -- generates a register EN OESS; EN two_dff; :,, : -- Solution 2: One FF IBAY ieee; USE ieee.std_logic_64.all; ENTITY dff IS OT ( d, clk: IN ST_OGI; q: BUFFE ST_OGI;

30 qbar: OUT ST_OGI); EN dff; AITETUE one_dff OF dff IS OESS (clk) IF (clk'event AN clk='') TEN q <= d; -- generates a register EN OESS; qbar <= NOT q; -- uses logic gate (no register) EN one_dff;, : count <= ; IF count < half TEN lk <= ''; ESE lk <= ''; EN OESS; EN Behavior; 3 ode. V behavioral description of a clock divider circuit. /FGAs, q qbar pins, o fitter (place & route) FFs.. fitter (place & route),.. V E. O. wang, igital ogic and Microprocessor esign withv. atches and Flip-Flops IBAY IEEE; USE IEEE.ST_OGI_64.A; ENTITY lockdiv IS OT ( lk25mhz: IN ST_OGI; lk: OUT ST_OGI); EN lockdiv; AITETUE Behavior OF lockdiv IS ONSTANT max: INTEGE := 25; ONSTANT half: INTEGE := max/2; SIGNA count: INTEGE ANGE TO max; OESS WAIT UNTI lk25mhz'event and lk25mhz = ''; IF count < max TEN count <= count + ; ESE