SMPS MOSFET. V DSS Rds(on) max I D
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- Gerard Webster
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1 Applications l Switch Mode Power Supply ( SMPS ) l Uninterruptable Power Supply l High speed power switching SMPS MOSFET PD 9885A IRFBC40A HEXFET Power MOSFET V DSS Rds(on) max I D 600V.2Ω 6.2A Benefits l Low Gate Charge Qg results in Simple Drive Requirement l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche Voltage and Current l Effective Coss Specified ( See AN 0) TO220AB G D S Absolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 6.2 I T C = 0 C Continuous Drain Current, V V 3.9 A I DM Pulsed Drain Current 25 P C = 25 C Power Dissipation 25 W Linear Derating Factor.0 W/ C V GS GatetoSource Voltage ± 30 V dv/dt Peak Diode Recovery dv/dt ƒ 6.0 V/ns T J Operating Junction and 55 to 50 T STG Storage Temperature Range C Soldering Temperature, for seconds 300 (.6mm from case ) Mounting torqe, 632 or M3 screw lbf in (.N m) Typical SMPS Topologies: l Single Transistor Forward Notes through are on page 8 6/24/99
2 T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS DraintoSource Breakdown Voltage 600 V V GS = 0V, I D = 250µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0.66 V/ C Reference to 25 C, I D = ma R DS(on) Static DraintoSource OnResistance.2 Ω V GS = V, I D = 3.7A V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µA I DSS DraintoSource Leakage Current 25 V µa DS = 600V, V GS = 0V 250 V DS = 480V, V GS = 0V, T J = 25 C I GSS GatetoSource Forward Leakage 0 V GS = 30V na GatetoSource Reverse Leakage 0 V GS = 30V T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 3.4 S V DS = 50V, I D = 3.7A Q g Total Gate Charge 42 I D = 6.2A Q gs GatetoSource Charge nc V DS = 480V Q gd GatetoDrain ("Miller") Charge 20 V GS = V, See Fig. 6 and 3 t d(on) TurnOn Delay Time 3 V DD = 300V t r Rise Time 23 ns I D = 6.2A t d(off) TurnOff Delay Time 3 R G = 9.Ω t f Fall Time 8 R D = 47Ω,See Fig. C iss Input Capacitance 36 V GS = 0V C oss Output Capacitance 36 V DS = 25V C rss Reverse Transfer Capacitance 7.0 pf ƒ =.0MHz, See Fig. 5 C oss Output Capacitance 487 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 36 V GS = 0V, V DS = 480V, ƒ =.0MHz C oss eff. Effective Output Capacitance 48 V GS = 0V, V DS = 0V to 480V Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energy 570 mj I AR Avalanche Current 6.2 A E AR Repetitive Avalanche Energy 3 mj Thermal Resistance Parameter Typ. Max. Units R θjc JunctiontoCase.0 R θcs CasetoSink, Flat, Greased Surface 0.50 C/W R θja JunctiontoAmbient 62 Diode Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 6.2 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 25 (Body Diode) pn junction diode. S V SD Diode Forward Voltage.5 V T J = 25 C, I S = 6.2A, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 6.2A Q rr Reverse RecoveryCharge µc di/dt = 0A/µs t on Forward TurnOn Time Intrinsic turnon time is negligible (turnon is dominated by L S L D ) 2
3 I D, DraintoSource Current (A) 0 0. VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V I D, DraintoSource Current (A) 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH T J = 25 C V DS, DraintoSource Voltage (V) 20µs PULSE WIDTH T 0. J = 50 C 0 V DS, DraintoSource Voltage (V) Fig. Typical Output Characteristics, Fig 2. Typical Output Characteristics, I D, DraintoSource Current (A) 0 T = 50 J C T J = 25 C V DS= 50V 20µs PULSE WIDTH V GS, GatetoSource Voltage (V) R DS(on), DraintoSource On Resistance (Normalized) I D = 5.9A 6.2A V GS = V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized OnResistance Vs. Temperature 3
4 C, Capacitance(pF) IRFBC40A V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss Coss Crss 0 00 V DS, DraintoSource Voltage (V) V GS, GatetoSource Voltage (V) I = D 6.2A 5.9A V DS = 480V V DS = 300V V DS = 20V FOR TEST CIRCUIT SEE FIGURE Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. DraintoSource Voltage Fig 6. Typical Gate Charge Vs. GatetoSource Voltage 0 0 OPERATION IN THIS AREA LIMITED BY R DS(on) I SD, Reverse Drain Current (A) T J = 50 C T J = 25 C V GS = 0 V V SD,SourcetoDrain Voltage (V) I D, Drain Current (A) us 0us ms ms TC = 25 C TJ = 50 C Single Pulse V DS, DraintoSource Voltage (V) Fig 7. Typical SourceDrain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4
5 7.0 V DS R D I D, Drain Current (A) R G V GS V Pulse Width µs Duty Factor 0. % D.U.T. Fig a. Switching Time Test Circuit V DD T, Case Temperature ( C C) Fig 9. Maximum Drain Current Vs. Case Temperature V DS 90% % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Thermal Response (Z thjc ) D = PDM t 0.05 t Notes: SINGLE PULSE (THERMAL RESPONSE). Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc TC t, Rectangular Pulse Duration (sec) Fig. Maximum Effective Transient Thermal Impedance, JunctiontoCase 5
6 V DSav, Avalanche Voltage ( V ) IRFBC40A R G V DS 20V tp Fig 2a. Unclamped Inductive Test Circuit tp L D.U.T I AS 0.0Ω V (BR)DSS 5V DRIVER V DD A E AS, Single Pulse Avalanche Energy (mj) TOP BOTTOM I D 2.8A 3.9A 6.2A Starting T, Junction Temperature ( J C) I AS Fig 2b. Unclamped Inductive Waveforms Q G Fig 2c. Maximum Avalanche Energy Vs. Drain Current V Q GS Q GD 820 V G 800 Current Regulator Same Type as D.U.T. Charge Fig 3a. Basic Gate Charge Waveform V V GS.2µF 50KΩ 3mA.3µF D.U.T. I G I D Current Sampling Resistors V DS Fig 3b. Gate Charge Test Circuit I AV, Avalanche Current ( A) Fig 2d. Typical DraintoSource Voltage Vs. Avalanche Current
7 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. Device Under Test V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD ReApplied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For NChannel HEXFETS 7
8 Package Outline TO220AB Outline Dimensions are shown in millimeters (inches) 2.87 (.3) 2.62 (.3).54 (.45).29 (.405) 3.78 (.49) 3.54 (.39) A 4.69 (.85) 4.20 (.65) B.32 (.052).22 (.048) 5.24 (.60 0) 4.84 (.58 4) (.2 55) 6. (.2 40) (.045) M IN LEAD ASSIGNMENTS GA T E 2 DR A IN 3 SOURCE 4 DR A IN 4.09 (.5 55) 3.47 (.5 30) 4.06 (.60) 3.55 (.40) EXAMPLE : 3X.40 (.055).5 (.045) 2.54 (.0) 2X 3X 0.93 (.03 7) 0.69 (.02 7) 0.36 (.0 4) M B A M 3X 2.92 (.5) 2.64 (.4) 0.55 (.022) 0.46 (.08) NOTES: DIMENSIONING & TOLERANCING PER ANSI Y4.5M, OUTLINE CONFORMS TO JEDEC OUTLINE TO220AB. 2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. Part Marking Information TO220AB THIS IS AN IRF W ITH ASSEMBLY LOT CODE 9BM INTERN ATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRF B M A PART NUMBER DATE CODE (YYWW) YY = YEAR WW = WEEK Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) Starting T J = 25 C, L =29.6mH R G = 25Ω, I AS = 6.2A. (See Figure 2) ƒ I SD 6.2A, di/dt 80A/µs, V DD V (BR)DSS, T J 50 C Pulse width 300µs; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (3) IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: IR CANADA: 5 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) IR GERMANY: Saalburgstrasse 57, 6350 Bad Homburg Tel: IR ITALY: Via Liguria 49, 07 Borgaro, Torino Tel: IR FAR EAST: K&H Bldg., 2F, 304 NishiIkebukuro 3Chome, ToshimaKu, Tokyo Japan 7 Tel: IR SOUTHEAST ASIA: Kim Seng Promenade, Great World City West Tower, 3, Singapore Tel: IR TAIWAN:6 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 673, Taiwan Tel: Data and specifications subject to change without notice. 6/99 8
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Features Advanced Process Technology New Ultra Low On-Resistance 75 C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax Lead-Free, RoHS Compliant Automotive Qualified * AUTOMOTIVE
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More informationC Soldering Temperature, for 10 seconds 300 (0.063 in. (1.6mm from case )
PD - 9657B INSULATED GATE BIPOLAR TRANSISTOR IRG4PC50W Features Designed expressly for Switch-Mode Power Supply and PFC (power factor correction) applications Industry-benchmark switching losses improve
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l LogicLevel Gate rive l dvanced Process Technology l ynamic dv/dt Rating l 75 C Operating Temperature l Fast Switching l Fully valanche Rated escription Fifth Generation HEXFETs from International Rectifier
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l dvanced Process Technology l Surface Mount (IRF4905S) l Lowprofile throughhole (IRF4905L) l 175 C Operating Temperature l Fast Switching l PChannel l Fully valanche Rated escription Fifth Generation
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