Introduction to Sequential Circuits

Transcription

1 Models of Digital Circuits Combinational Logic : Output states of Combinational Logic depends only on the current states of input variables. equential Logic : Next Output state (n+) of equential Logic depends on the current state of input variables and current output state (n). We need a Memory element for old (previous) state. Latch Flip-Flop Delay Output state Inputs Clock Current state Next Current n n+ n+2 If memory element is clocked, then circuit is synchrous, if not, circuit is asynchronous.

2 Models of Digital Circuits n input variables Combinational Logic m output variables 2

3 Models of Digital Circuits Model for sequential logic n input variables x x 2 z z 2 m output variables x n Combinational circuit z m k secondary variables (present state) y y 2 Y Y 2 k exitation variables (next state) y k Y k Clock used/not used depends on applications Memory Memory Memory 3

4 Models of Digital Circuits ynchronous sequential logic Asynchronous sequential logic CLK INPUT INPUT OUT A OUT A OUT B OUT B The change of internal state occurs in response to the clock pulses. Memory element : clocked, (gated) The change of internal state occurs when there is change in the input variables. Memory element : unclocked or time-delay elements. 4

5 ynchronous or asynchronous? ynchronous sequential logic Asynchronous sequential logic Properly designed system No clocked flip-flops Feedback bath "No timing problems" Timing problems The design of asynchronous sequential circuits is difficult Used when speed of operation is important Fast response to the change of input variable No clock distribution edused logic and power dissipation 5

6 Models of Digital Circuits Wery Important for Asynchronous equential Logic. To ensure proper operation, circuits must be allowed to attain a stable state before the input is changed to a new value. Because of delays in the wires and the gate circuits it is "impossible" to say which variable changes its state first when two or more input variables change at "exactly same instant time". Fundamental mode Input signals change one at a time and only when the circuit is in the stable state. In this course material we design and analyze only synchronous sequential logic. 6

7 Mealy Type state Machine Output is a function of both the present state and the input. Inputs Next tate Combinational Logic Clock Memory Output Combinational Logic Outputs Asynchronous outputs Exitation equations tate egisters Typically, D flip-flops are used by synthesis tools. Block diagram of Mealy type state machine 7

8 Mealy Type state Machine Inputs Next tate Combinational Logic Clock tate egisters Output Combinational Logic Outputs Present input/present output Present states A(t) B(t) Present input x(t) Next states A(t+) B(t+) Present output y(t) t t+ t ABx AB y tate table of Mealy FM Present state x(t)/y(t) x(t+)/y(t+) A(t)B(t) A(t+)B(t+) x(t)/y(t) Next state tate after the clock cycle Clock tate diagram 8

9 Mealy Type state Machine Example : input/output t t+ t ABx AB y tate table of Mealy FM Present state x(t)/y(t) Clock Present input/present output x(t)/y(t) Next state A(t)B(t) A(t+)B(t+) tate after the clock cycle A,B / / / / / / / / tate diagram of Mealy FM 9

10 Moore Type state Machine Output is only a function of the present state. Present Outputs Next tates Inputs Next tate Combinational Logic Exitation equations Clock Present tates Memory tate egisters Output Combinational Logic Outputs Asynchronous outputs Typically D flip-flops are used by synthesis tools. Block diagram of Moore type state machine

11 Moore Type state Machine Example : t t+ t ABx AB y tate table of Moore FM Present Input tate/output t x Clock tate Next state t+ x= / / / / AB/y tate diagram

12 torage elements Latches torage elements that operate with signal levels are referred to as latches. latch with NAND gates latch with NO gates latch with control input C D latch with control input C (Transparent latch) 2

13 torage elements Allowed input transitions in fundamental mode n + = + = n n n + = + = n n + = + = n = n =?? tate table n + n n + n Latch latch with NO gates Function table of latch with NO gates reset state set state? = or Depends on previous state "forced" states: reset and set ymbol ymbol 3

14 torage elements Latch latch with NAND gates?? tate table "forced" states: reset and set? = or Depends on previous state n + n n + n set state reset state ymbol Function table of latch with NAND gates ymbol 4

15 torage elements Latch latch with NAND gates n + n n + n Function table of latch with NAND gates In general, the function table of latch n + n?? = / Depend on latch implementation ymbol 5

16 torage elements Latch et-reset latch timing diagram With zero-delay model With non-zero-delay model 6

17 torage elements Latch latch with Control input C n + n n + n set state reset state Function table of latch with NAND gates C n + + n n n X X n Function table of gated latch with NAND gates n reset state set state C= C ymbol 7

18 torage elements D Latch D latch with Control input (Transparent latch) C n + + n n n X X n Function table of gated latch with NAND gates n reset state set state Assumption : C D = D C ymbol 8

19 torage elements D Latch D latch with Control input (Transparent latch) D D C n + n + X X n n reset state set state C D X n + n reset state set state storage state Function table of gated D latch "Transparent mode" when C = Hold Enable Hold C torage mode Transparent torage mode D Present state Next state n n + 9

20 torage elements D Latch D Latch Timing Constrains D t su C t su t h t h Hold time violation t w etup time violation D may not change t w Minimum pulse width of the gate signal (clock) t su etup Time t h Hold Time 2

21 torage elements Latches A simple application of -latch n + n n + n set state reset state Function table of latch with NAND gates +5V W in position W in position 2 2 W 2

22 The End 22