Chapter 5 Bistable memory devices. Copyright The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
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1 Chapter 5 Bistable memory devices Copyright The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
2 Digital circuits Combinational Sequential Logic gates Decoders, MUXes, Adders, Multipliers Bistable elements Registers, Counters, Memories
3 Setting and Resetting a light switch
4 Setting and Resetting a light switch
5 5.2 The S-R NOR latch
6 Analysis
7 Truth table is now called characteristic table
8 Boolean equation is now called characteristic equation
9 QUIZ Write the characteristic eq. for this circuit
10 More detailed analysis: PS/NS table
11 QUIZ Write the PS/NS table for this circuit (NAND-NAND latch) Q R Q S
12 Compare with the previous S-R latch What do you notice? Q R Q S
13 The NAND-NAND latch is also known as the non-s-non-r latch Q R Q S
14 Timing diagram
15 P 5.19: Draw the waveform for the output Q of the S-R latch
16 VHDL
17 VHDL alternative code Local variable!
18 To do for next time Read carefully Section 5.2 Solve in notebook end-of-chapter 1-15.
19 5.3 S-R NAND latch Q R Q S
20 Characteristic table Q R Q S
21 Characteristic table PS/NS table
22 WAVEFORM 5.3
23 P 5.30: Complete the timing diagram for the non S-non R latch
24 Q R Q S R Q S
25 Note well: In the NOR-NOR latch, the state/output Q is on the side of R, but in the NAND-NAND it is on the side of S!
26 QUIZ Do you recognize the boxed parts below?
27 5.4 An even simpler sequential circuit: CLK generator
28
29 WAVEFORM 5.5
30 Controlling the CLK period
31 QUIZ In order for the switching to occur in a CMOS inverter, the input must reach a level that is 30% away from its final value, i.e. 70% if going high and 30% if going low. We have R = 1kW and we want f = 9.09 khz. What value should we choose for C?
32 What happens when DISABLE = 1? DISABLE = 0?
33 QUIZ: Draw the circuit diagram for this VHDL code!
34 Crystal CLK generators are much more precise than solid-state ones! Source:
35 Next time we re going to start building
36 To do for next time Read carefully Sections 5.3 and 5.4 Solve in notebook end-of-chapter 17, 24-27, 39.
37 5.5 D latch Step 1: Gated S-R latch
38 FIGURE 5.12 Step 2: Avoid forbidden combinations
39 Characteristic table and PS/NS table for D latch
40 We can design the D latch from scratch, by minimizing the next state logic from the PS/NS table! Do you recognize this circuit?
41 Implementing a D latch with a MUX
42 The Enable input C is usually connected to a CLK signal
43 LISTING 5.4
44 The nitty-gritty: propagation delays and feedback make possible glitches and metastable states To avoid these hazards, the D input is not allowed to change within the setup time and hold time
45 Example of use for D latch: N-bit Register
46 How not to use a D-latch: Stoppable clock Problem: When C is 1, the external feedback loop causes D and Q to oscillate very fast until C goes to 0, at which time a setup time violation will cause a glitch or metastability. Wish: Could we make the CLK active on edge rather than level?
47 Review of latches Transparent: S-R, non-s-non-r Changes in inputs propagate always to the state Q Gated: gated S-R, gated non-s-non-r, D Changes in inputs propagate to the state Q only during the positive level of CLK Can we make the validation even more precise? Yes, let s allow the inputs to propagate only on the edge of CLK!
48 5.6 D Flip-Flop Master-slave design In order for the circuit to be glitch-free, the master must be hazard-free!
49 We repeat the K-map design of the D latch, but making it hazard-free!
50 The S-R and non-s-non-r implementations of the D latch are naturally hazard-free, so they can be slightly modified to accept the CLR input:
51 The S-R and non-s-non-r implementations of the D latch are naturally hazard-free, so they can be slightly modified to accept the CLR input:
52 The S-R and non-s-non-r implementations of the D latch are naturally hazard-free, so they can be slightly modified to accept the CLR input: Excellent review question: Prove, using K-maps, that they are hazard-free!
53 Characteristic table for the D Flip-Flop
54 Read over lightly pages We retain only the following facts: We can design D flip-flops with PRESET input
55 Read over lightly pages We retain only the following facts: We can design D flip-flops triggered on the NEGATIVE edge of CLK, with PRESET and/or CLR inputs
56 Extra-credit: Draw the master-slave diagram for the negative edge triggered D FF?
57 If this timing diagram for positive edge of negative edge D FF?
58 P5.90 Complete the timing diagram for positive edge-triggered FF
59 Complete the timing diagram for negative edge-triggered FF
60 Draw the characteristic table for this circuit
61 Draw the characteristic table for this circuit
62 Draw the characteristic table for this circuit
63 Draw the characteristic table for this circuit This is called a T flip-flop
64 Homework for Ch.5, due Wednesday, March 18 16, 19*, 30*, 27, 31, 35, 38, 60, 68, 76, 84, 85, 91** * Since we solved both P.19 and P.30 as quizzes in class, swap the two waveforms, as shown on the next two slides. **For P.91, use the timing diagram provided on the last slide. All homework assignments are also available on the course webpage.
65 Waveform from P 5.30, to be used in the homework for P 5.19
66 Waveform from P 5.19, to be used in the homework for P 5.30
67 FIGURE P5.91
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