Lecture 7: Sequential Networks
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1 Lecture 7: Sequential Networks CSE 14: Components and Design Techniques for Digital Systems Fall 214 CK Cheng Dept. of Computer Science and Engineering University of California, San Diego 1
2 What is a sequential circuit? A circuit whose output depends on current inputs and past outputs A circuit with memory 2
3 Part II. Sequential Networks (Ch. 3) Memory / Time steps x i s i y i Clock y i = f i (S t,x) Memory: Flip flops s t+1 i = g i (S t,x) Specification: Finite State Machines Implementation: Excitation Tables Main Theme: Timing Present time = t and next time = t+1 Timing constraints to separate the present and next times. 3
4 Sequential Networks Memory Components Hierarchy of Memory Basic Mechanism of Memory Types of Flip-Flops Implementation Finite State Machine 4
5 The usage of a sequential machine iclicker uestion: A. Digital systems are implemented using sequential machines. B. Only a small subset of digital systems can be implemented using sequential machines. C. Sequential machines are too simple for complicated digital systems. 5
6 Hierarchy of Memory Devices Memory Bank (Farms of memory cells) egister (A vector of memory cells) Flip-Flop (One bit memory cell) S, D, T, JK flip-flops (Different types of memory cells) State Tables (Truth table of sequential machine) Characteristic Expressions (Switching algebraic expression of sequential machine) 6
7 Fundamental Memory Mechanism I2 I1 I1 I2 7
8 Memory Mechanism: Capacitive Load Fundamental building block of sequential circuits Two outputs:, There is a feedback loop! In a typical combinational logic, there is no feedback loop. No inputs I2 I1 I1 I2 8
9 Capacitive Loads Consider the two possible cases: = : then = 1 and = (consistent) 1 I1 I2 1 = 1: then = and = 1 (consistent) I1 1 1 I2 Bistable circuit stores 1 bit of state in the state variable, (or ) But there are no inputs to control the state 9
10 iclicker. Given a memory component made out of a loop of inverters, the number of inverters has to be A. Even B. Odd 1
11 S (Set/eset) Latch S Latch N1 S N2 Consider the four possible cases: S = 1, = S =, = 1 S =, = S = 1, = 1 11
12 S Latch Analysis S = 1, = : N1 S 1 N2 S =, = 1: 1 N1 S N2 12
13 S Latch Analysis S = 1, = : then = 1 and = N1 S 1 N2 S =, = 1: then = and = 1 1 N1 S N2 13
14 S Latch Analysis S = 1, = 1: 1 N1 S 1 N2 14
15 S Latch Analysis S =, = : N1 S N2 15
16 S Latch Analysis S =, = : then = prev prev = prev = 1 N1 N1 S N2 S N2 S = 1, = 1: then = and = 1 N1 S 1 N2 16
17 S y y = (S+) = (+y) 17
18 Flip-flop Components S F-F (Set-eset) S y Inputs: S, State: (, y) 18
19 Id (t) y(t) S (t 1 ) y(t 1 ) (t 2 )y(t 2 ) (t 3 ) y(t 3 ) S 11 State y State Diagram Transition S 19
20 CASES: S=1, (,y) = (,1) S=1, (,y) = (1,) S=11, (,y) = (,) S = => if (,y) = (,) or (1,1), the output keeps changing. To avoid the S latch output from toggling or behaving in an undefined way which input combinations should be avoided: A. (S, ) = (, ) B. (S, ) = (1, 1) 2
21 S Latch Analysis S =, = : then = prev and = prev (memory!) prev = prev = 1 1 N1 N1 1 S N2 1 S 1 N2 S = 1, = 1: then = and = (invalid state: NOT ) 1 N1 S 1 N2 21
22 CASES S=1: (,y) = (,1) S=1: (,y) = (1,) S=11: (,y) = (,) S = : if (,y) = (,) or (1,1), the output keeps changing Solutions: Avoid the two cases 1) S = (,), 2) S = (1,1). inputs PS (t) State table S Characteristic Expression (t+1) = S(t)+ (t)(t) (t+1) NS (next state) 22
23 S Latch Symbol S stands for Set/eset Latch Stores one bit of state () Control what value is being stored with S, inputs Set: Make the output 1 (S = 1, =, = 1) eset: Make the output (S =, = 1, = ) Must do something to avoid invalid state (when S = = 1) S Latch Symbol S 23
24 D Latch Two inputs:, D : controls when the output changes D (the data input): controls what the output changes to Function When = 1, D passes through to (the latch is transparent) When =, holds its previous value (the latch is opaque) Avoids invalid case when NOT D Latch Symbol D 24
25 D Latch Internal Circuit S Latch Symbol S D 25
26 D Latch Internal Circuit D D S S D D X D S 26
27 D Latch Internal Circuit D D D S S D X D X 1 S prev prev 27
28 D Flip-Flop Two inputs:, D Function The flip-flop samples D on the rising edge of When rises from to 1, D passes through to Otherwise, holds its previous value changes only on the rising edge of A flip-flop is called an edge-triggered device because it is activated on the clock edge D D Flip-Flop Symbols 28
29 D Flip-Flop Internal Circuit D D N1 D L1 L2 29
30 D Flip-Flop Internal Circuit Two back-to-back latches (L1 and L2) controlled by complementary clocks When = L1 is transparent, L2 is opaque D passes through to N1 When = 1 L2 is transparent, L1 is opaque N1 passes through to D D L1 Thus, on the edge of the clock (when rises from 1) D passes through to N1 D L2 3
31 D Flip-Flop vs. D Latch D D D (latch) (flop) 31
32 D Flip-Flop vs. D Latch D D D (latch) (flop) 32
33 Latch and Flip-flop (two latches) A latch can be considered as a door =, door is shut = 1, door is unlocked A flip-flop is a two door entrance = 1 = = 1 33
34 D Flip-Flop (Delay) D D D L1 N1 D L2 Id D (t) (t+1) State table PS D NS= (t+1) Characteristic Expression: (t+1) = D(t) 34
35 iclicker Can D flip-flip serve as a memory component? A.Yes B.No 35
36 JK F-F J K State table PS JK ? 1 1 1? (t+1) 36
37 JK F-F J K State table PS JK (t+1) Characteristic Expression (t+1) = (t)k (t)+ (t)j(t) 37
38 T Flip-Flop (Toggle) T State table PS T (t+1) Characteristic Expression (t+1) = (t)t(t) + (t)t (t) 38
39 Using a JK F-F to implement a D and T F-F x J K iclicker What is the function of the above circuit? A. D F-F B. T F-F C. None of the above 39
40 Using a JK F-F to implement a D and T F-F T J K T flip flop 4
41 eading [Harris] Chapter 3: 3.3, 3.4.1,
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