SELECT INPUTS STROBE OUTPUTS
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1 I SN x1 U SN74153 ( ), ogic Is-MUs MUX. SEET DT INPUTS STROE OUTPUT INPUTS G Y X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1. SN : SEET INPUTS STROE OUTPUT G Y X X SN I SN x1 U G D D1 D2 D3 D4 D5 D6 D7 2. SEET STROE OUTPUTS INPUTS G Y W X X X D D D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 3. SN o I SN x1 U G E E1 E2 E3 E4 E5 E6 E7 E8 E9 E1 E11 E12 E13 E14 E15 D W Y W 3. SEET INPUTS STROE OUTPUTS D G W X X X X E E1 E2 E3 E4
2 E5 E6 E7 E8 E9 E1 E11 E12 E13 E14 E15 4. SN (MUX 4x1 (x2)) ( 4), 1 ( 5). S1--(2) S--(1) 4. U S1--(2) S--(1) ~~ X X X 1 X X X 1 X X X 1 X 1 X X 1 X X X 1 X X 1 X 1 1 X X X 1 1 X X X 1 1 X X X 1 1 X X X 1 1 X X X 1 1 X 1 X X 1 1 X X X 1 1 X X 1 X X X X X X X (MUX 8x1), ( 5) oole oole. G D D1 D2 D3 D4 D5 D6 D7 S2--(4) U G D D1 D2 D3 D4 D5 D6 D7 S1--(2) D ( ),,, 2 3 x1 MUX. 3. ( D ),, F. - S--(1) Y W 1
3 MUX. MUX 4x1 (74153) : = (,3,6,7) = = =1 ( 6, 7) 1 select, 2 1. select 74153,. MUX = 1. 1 ( 6) select.,, MUX Z (2) (1) (2) (1) U2 SN744 U3 U U Number Z Z= = U Z Z=S(,3,6,7) i ( 2) (1 4) 8. i n o ut 1 MUX.4x1 (,,,1 3,) (1)= (7) = out Su m 1 1 (6)= (5)=in (4)=in (3)= MUX.4x1 (2,21,22,2 3,) (15)= (9)=Sum 2(1)=in 21(11)=in' 22(12)=in' 23(13)=in 3. MU. MUX 4x1(74153) : = (,1,3,8,9,1,15).
4 (D, ) select. 4 Z=Z(, ) ( 8). Number D Z Z= = = = 1 = = 2 = = 3 = MUX. MUX 8x1(74151) : = (,1,3,8,9,1,15) D(4)=1 D1(3)=D D2(2)= D3(1)= D4(15)=1 D5(14)=D D6(13)= D7(12)=D F1 = (,3,4,5,7) F2 = (2,3,5,7). i (x4) MUX = (x2) MUX = (x 1) F1 MUX=( ) = 2 1 = = = (x4) (x2) (x1) U2 SN744 ' 1. 1 ' U F2 MUX=( ) 2 = 1 21 =1 22 = 23 = F1 F2 9. i (9) (1) (11) D Z Y(5) G (7)= 6. F. F U U
5 ' F 1. 7., NOT, ND, OR, XOR XNOR, D, R 8. MUX F = D + + D VD MUX2x1 --Dataflow level VD description for the 2-input multiplexer ENTITY multiplexer IS PORT(d, d1, s: IN IT; y: OUT IT); END multiplexer; RITETURE Dataflow OF multiplexer IS y <= d WEN s = '' ESE d1; END Dataflow; 1. MUX2x1 U2 Full dder in in in U3!XOR U5 SN742 Full dder 2k N 1k out S G U6 5 U ehavioral level VD description for the 2- input multiplexer ENTITY multiplexer IS PORT (d, d1, s: IN IT; y: OUT IT); END multiplexer; RITETURE ehavioral OF multiplexer IS PROESS(s, d, d1) y <= d WEN s = '' ESE d1; END PROESS; END ehavioral; 2. MUX2x1 --Structural level VD description for the 2- input multiplexer ENTITY myand2 IS PORT (i1, i2: IN IT; o: OUT IT); END myand2; RITETURE Dataflow OF myand2 IS o <= i1 ND i2; END Dataflow; ENTITY myor2 IS PORT (i1, i2: IN IT; o: OUT IT); END myor2; RITETURE Dataflow OF myor2 IS o <= i1 OR i2; END Dataflow; ENTITY myinv IS PORT (i: IN IT; o: OUT IT); END myinv; RITETURE Dataflow OF myinv IS o <= not i; END Dataflow; ENTITY multiplexer IS PORT (d, d1, s: IN IT;y: OUT IT); END multiplexer; RITETURE Structural OF multiplexer IS OMPONENT myand2 PORT (i1, i2: IN IT;o: OUT IT); END OMPONENT; OMPONENT myor2 PORT (i1, i2: IN IT; o: OUT IT); END OMPONENT; OMPONENT myinv PORT (i: IN IT; o: OUT IT); END OMPONENT; SIGN sn, asn, sb: IT; U1: myinv PORT MP(s, sn); U2: myand2 PORT MP(d, sn, asn); U3: myand2 PORT MP(s, d1, sb); U4: myor2 PORT MP(asn, sb, y); END Structural; 3. :
6 : IRRY ieee; 3 USE ; ENTITY mux IS 6 PORT (, : STD_OGI_VETOR (7 DOWNTO ); 7 sel : IN ; 8 : OUT STD_OGI_VETOR (7 DOWNTO )); 9 END ; RITETURE example OF IS PROESS (a, b, ) IF (sel = "") TEN 16 c <= ""; 17 ESIF ( ) TEN 18 c <= a; 19 (sel = "1") TEN 2 c <= ; 21 ESE 22 c <= (OTERS => ' '); 23 END ; 24 END ; 25 END ; (oncurrent) VD VD (concurrent) VD WEN GENERTE., (ND, NOT, +, *, S ) OK,.,,.. RM :, RM VD PROESS, FUNTION PROEDURE., (dataflow code).,, ( GURDED OK). ( ),, PROESSES, 6
7 7 FUNTION PROEDURES. WEN GENER TE. VD. : NOT, ND, NND, OR, NOR, XOR, XNOR þ, _, *, /, ** (mod, rem, abs) =,/=,<,>,< =,>= sll, srl, sla, sra, rol, ror &, ( ) IT, IT_VETOR, STD_OGI, STD_OGI_VE TOR, STD_UOGI, STD_UOGI_VE TOR INTEGER, SIGNED, UNSIGNED IT_VETOR SIGNED UNSIGNED,, 4x1 : 1bit., s1 s. : IRRY ieee; ENTITY mux IS PORT ( a, b, c, d, s, s1: IN STD_OGI; y: OUT STD_OGI); END mux; RITETURE pure_logic OF mux IS y <= (a ND NOT s1 ND NOT s) OR (b ND NOT s1 ND s) OR (c ND s1 ND NOT s) OR (d ND s1 ND s); END pure_logic; WEN WEN ( GENERTE). : WEN/ESE ( WEN) WIT / SEET/WEN (selected WEN). : WEN / ESE: assignment WEN condition ESE assignment WEN condition ESE ; WIT / SEET / WEN: WIT identifier SEET assignment WEN value, assignment WEN value, ; WIT/SEET/WEN,, OTERS UNFFETED, : With WEN/ESE outp <= "" WEN (inp='' OR reset='1') ESE "1" WEN ctl='1' ESE "1"; ---- With WIT/SEET/WEN WIT control SEET output <=
8 "" WEN reset, "111" WEN set, UNFFETED WEN OTERS; WEN WEN value, : WEN value -- single value WEN value1 to value2 -- range, for enumerated data types -- only WEN value1 value2 -- value1 or value2 or WEN WEN/ESE: IRRY ieee; ENTITY mux IS PORT ( a, b, c, d: IN STD_OGI; sel: IN STD_OGI_VETOR (1 DOWNTO ); y: OUT STD_OGI); END mux; RITETURE mux1 OF mux IS y <= a WEN sel="" ESE b WEN sel="1" ESE c WEN sel="1" ESE d; END mux1; WEN/SEET/WEN: IRRY ieee; ENTITY mux IS PORT ( a, b, c, d: IN STD_OGI; sel: IN STD_OGI_VETOR (1 DOWNTO ); y: OUT STD_OGI); END mux; RITETURE mux2 OF mux IS WIT sel SEET y <= a WEN "", -- notice "," instead of ";" b WEN "1", c WEN "1", d WEN OTERS; -- cannot be "d WEN "11" END mux2;, sel INTEGER, : WEN/ESE: IRRY ieee; ENTITY mux IS PORT ( a, b, c, d: IN STD_OGI; sel: IN INTEGER RNGE TO 3; y: OUT STD_OGI); END mux; ---- Solution 1: with WEN/ESE RITETURE mux1 OF mux IS y <= a WEN sel= ESE b WEN sel=1 ESE c WEN sel=2 ESE d; END mux1; -- Solution 2: with WIT/SEET/WEN RITETURE mux2 OF mux IS WIT sel SEET y <= a WEN, b WEN 1, c WEN 2, d WEN 3; -- here, 3 or OTERS are equivalent, -- for all options are tested anyway END mux2;, RITETURE, ( --), (synthesis script),, ONFIGURTION (tristate buffer) WEN. output = input ena=low output =» ( ) : IRRY ieee; ENTITY tri_state IS 8
9 9 PORT ( ena: IN STD_OGI; input: IN STD_OGI_VETOR (7 DOWNTO ); output: OUT STD_OGI_VETOR (7 DOWNTO )); END tri_state; RITETURE tri_state OF tri_state IS output <= input WEN (ena='') ESE (OTERS => 'Z'); END tri_state; WEN : IRRY ieee; ENTITY encoder IS PORT ( x: IN STD_OGI_VETOR (7 DOWNTO ); y: OUT STD_OGI_VETOR (2 DOWNTO )); END encoder; RITETURE encoder2 OF encoder IS WIT x SEET y <= "" WEN "1", "1" WEN "1", "1" WEN "1", "11" WEN "1", "1" WEN "1", "11" WEN "1", "11" WEN "1", "111" WEN "1", "ZZZ" WEN OTERS; END encoder2; U (rithmetic ogic Unit) : n 2, m=log 2 n. bit high WEN/ESE: IRRY ieee; ENTITY encoder IS PORT ( x: IN STD_OGI_VETOR (7 DOWNTO ); y: OUT STD_OGI_VETOR (2 DOWNTO )); END encoder; RITETURE encoder1 OF encoder IS y <= "" WEN x="1" ESE "1" WEN x="1" ESE "1" WEN x="1" ESE "11" WEN x="1" ESE "1" WEN x="1" ESE "11" WEN x="1" ESE "11" WEN x="1" ESE "111" WEN x="1" ESE "ZZZ"; END encoder1; WIT/SEET/WEN: : sel Operation Function Unit y <= a Transfer a rithmetic 1 y <= a+1 Increment a 1 y <= a-1 Decrement a 11 y <= b Transfer b 1 y <= b+1 Increment b 11 y <= b-1 Decrement b 11 y <= a+b dd a and b 111 y <= a+b+cin dd a and b with carry 1 y <= NOT a omplement ogic a 11 y <= NOT b omplement b 11 y <= a ND b ND 111 y <= a OR b OR 11 y <= a NND b NND 111 y <= a NOR b NOR 111 y <= a XOR b XOR 1111 y <= a XNOR b XNOR
10 ( ) MS sel, bits sel. U,, std_logic_unsigned ieee. arith logic IRRY ieee; USE ieee.std_logic_unsigned.all; ENTITY U IS PORT (a, b: IN STD_OGI_VETOR (7 DOWNTO ); sel: IN STD_OGI_VETOR (3 DOWNTO ); cin: IN STD_OGI; y: OUT STD_OGI_VETOR (7 DOWNTO )); END U; RITETURE dataflow OF U IS SIGN arith, logic: STD_OGI_VETOR (7 DOWNTO ); rithmetic unit: WIT sel(2 DOWNTO ) SEET arith <= a WEN "", a+1 WEN "1", a-1 WEN "1", b WEN "11", b+1 WEN "1", b-1 WEN "11", a+b WEN "11", a+b+cin WEN OTERS; ogic unit: WIT sel(2 DOWNTO ) SEET logic <= NOT a WEN "", NOT b WEN "1", a ND b WEN "1", a OR b WEN "11", a NND b WEN "1", a NOR b WEN "11", a XOR b WEN "11", NOT (a XOR b) WEN OTERS; Mux: WIT sel(3) SEET y <= arith WEN '', logic WEN OTERS; END dataflow; GENERTE 1 GENERTE ( WEN). OOP, FOR / GENERTE (label): label: FOR identifier IN range GENERTE (concurrent assignments) END GENERTE; IF / GENERTE ( IF ). ESE. IF / GENERTE FOR / GENERTE : label1: FOR identifier IN range GENERTE label2: IF condition GENERTE (concurrent assignments) END GENERTE; END GENERTE; : SIGN x: IT_VETOR (7 DOWNTO ); SIGN y: IT_VETOR (15 DOWNTO ); SIGN z: IT_VETOR (7 DOWNTO ); G1: FOR i IN x'rnge GENERTE z(i) <= x(i) ND y(i+8); END GENERTE; GENERTE ( OOP),, choice -, : NotOK: FOR i IN TO choice GENERTE (concurrent statements) END GENERTE;,.. : OK: FOR i IN TO 7 GENERTE output(i)<='1' WEN (a(i) ND b(i))='1' ESE ''; END GENERTE;
11 11 : NotOK: FOR i IN TO 7 GENERTE accum <=" " WEN (a(i) ND b(i))='1' ESE ""; END GENERTE; NotOK: For i IN to 7 GENERTE accum <= accum + 1 WEN x(i)='1'; END GENERTE;, GENERTE., : IRRY ieee; ENTITY shifter IS PORT ( inp: IN STD_OGI_VETOR (3 DOWNTO ); sel: IN INTEGER RNGE TO 4; outp: OUT STD_OGI_VETOR (7 DOWNTO )); END shifter; RITETURE shifter OF shifter IS SUTYPE vector IS STD_OGI_VETOR (7 DOWNTO ); TYPE matrix IS RRY (4 DOWNTO ) OF vector; SIGN row: matrix; row() <= "" & inp; G1: FOR i IN 1 TO 4 GENERTE row(i) <= row(i-1)(6 DOWNTO ) & ''; END GENERTE; outp <= row(sel); END shifter; OK OK: Simple Guarded., OK : label: OK [declarative part] (concurrent statements) END OK label; - : RITETURE example block1: OK END OK block1 block2: OK END OK block2; END example; : b1: OK SIGN a: STD_OGI; a <= input_sig WEN ena='1' ESE 'Z'; END OK b1; OK, (simple guarded) OK. : label1: OK [declarative part of top block] [concurrent statements of top block] label2: OK [declarative part nested block] (concurrent statements of nested block) END OK label2; [more concurrent statements of top block] END OK label1; guarded OK OK,, guard expression. OK TRUE: label: OK (guard expression) [declarative part] (concurrent guarded and unguarded statements) END OK label; OK, OK,
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