MC14175B/D. Quad Type D Flip-Flop

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1 Quad Type D Flip-Flop The MC475B quad type D flipflop is cotructed with MOS Pchannel and Nchannel enhancement mode devices in a single monolithic structure. Each of the four flipflops is positiveedge triggered by a common clock input (C). An activelow reset input (R) asynchronously resets all flipflops. Each flipflop has independent Data (D) inputs and complementary outputs (Q and Q). These devices may be used as shift register elements or as type T flipflops for counter and toggle applicatio. Features Complementary Outputs Static Operation All Inputs and Outputs Buffered Diode Protection on All Inputs Supply Voltage Range = 3.0 to 8 Output Compatible with Two LowPower TTL Loads or One LowPower Schottky TTL Load Functional Equivalent to TTL 7475 These Devices are PbFree and are RoHS Compliant NLV Prefix for Automotive and Other Applicatio Requiring Unique Site and Control Change Requirements; AEC Qualified and PPAP Capable* MAXIMUM RATINGS (Voltages Referenced to V SS ) Parameter Symbol Value Unit DC Supply Voltage Range V DD 0.5 to +8.0 V Input or Output Voltage Range (DC or Traient) Input or Output Current (DC or Traient) per Pin V in, V out 0.5 to V DD I in, I out ± ma Power Dissipation per Package (Note ) P D 500 mw Ambient Temperature Range T A 55 to +25 C Storage Temperature Range 65 to +0 C Lead Temperature (8Second Soldering) 260 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.. Temperature Derating: D/DW Packages: 7.0 mw/ C From 65 C To 25 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, V in and V out should be cotrained to the range V SS (V in or V out ) V DD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V SS or V DD ). Unused outputs must be left open. V 6 SOIC6 D SUFFIX CASE 75B ORDERING INFORMATION Device Package Shipping MC475BDG MC475BDR2G MC475BFELG MARKING DIAGRAMS 475BG AWLYWW SOIC6 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = PbFree Package NLV475BDR2G* PIN ASSIGNMENT R D0 D Q Q V SS SOIC6 (PbFree) SOIC6 (PbFree) SOIC6 (PbFree) SOEIAJ6 (PbFree) SOEIAJ6 F SUFFIX CASE 966 V DD D3 D2 C MC475B ALYWG SOEIAJ6 48 Units/Rail 2500/Tape & Reel 2500/Tape & Reel 00/Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BRD/D. Semiconductor Components Industries, LLC, 4 August, 4 Rev. 9 Publication Order Number: MC475B/D

2 9 CLOCK 2 TRUTH TABLE Inputs Outputs Clock Data Reset Q Q X Q Q X X 0 0 X = Don t Care No Change RESET D0 D D2 D3 Q Q V DD = PIN 6 V SS = PIN 8 Figure. Block Diagram Figure 2. Timing Diagram Figure 3. Functional Block Diagram 2

3 ELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS ) Characteristic Output Voltage V in = V DD or 0 V in = 0 or V DD 0 Level Level Input Voltage 0 Level (V O = 4.5 or 0.5 ) (V O = 9.0 or.0 ) (V O = 3.5 or.5 ) Level (V O = 0.5 or 4.5 ) (V O =.0 or 9.0 ) (V O =.5 or 3.5 ) Output Drive Current (V OH = 2.5 ) Source (V OH = 4.6 ) (V OH = 9.5 ) (V OH = 3.5 ) (V OL = 0.4 ) Sink (V OL = 0.5 ) (V OL =.5 ) V DD Symbol V OL V OH V IL V IH I OH I OL 55 C 25 C 25 C Min Max Min Typ (Note 2) Max Min Max Unit madc madc Input Current I in ±0. ± ±0. ±.0 Adc Input Capacitance (V in = 0) C in 7.5 pf Quiescent Current (Per Package) I DD Adc Total Supply Current (Notes 3 & 4) (Dynamic plus Quiescent, Per Package) (C L = 50 pf on all outputs, all buffers switching) I T I T = (.7 A/kHz) f + I DD I T = (3.4 A/kHz) f + I DD I T = ( A/kHz) f + I DD Product parametric performance is indicated in the Electrical Characteristics for the listed test conditio, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditio. 2. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance. 3. The formulas given are for the typical characteristics only at 25 C. 4. To calculate total supply current at loads other than 50 pf: I T (C L ) = I T (50 pf) + (C L 50) Vfk where: I T is in A (per package), C L in pf, V = (V DD V SS ) in volts, f in khz is input frequency, and k = Adc 3

4 SWITCHING CHARACTERISTICS (Note 5) (C L = 50 pf, T A = 25 C) Characteristic Output Rise and Fall Time t TLH, t THL = (.35 /pf) C L + 32 t TLH, t THL = (0.6 /pf) C L + t TLH, t THL = (0.4 /pf) C L + Propagation Delay Time Clock to Q, Q t PLH, t PHL = (0.9 /pf) C L + 75 t PLH, t PHL = (0.36 /pf) C L + 72 t PLH, t PHL = (0.26 /pf) C L + 57 Propagation Delay Time Reset to Q, Q t PHL = (0.9 /pf) C L + 2 t PHL = (0.36 /pf) C L + 2 t PHL = (0.26 /pf) C L + 87 Symbol V DD t TLH, t THL t PLH, t PHL t PHL, t PLH Clock Pulse Width t WH Reset Pulse Width t WL Clock Pulse Frequency f cl Clock Pulse Rise and Fall Time t TLH, t THL Data Setup Time t su Data Hold Time t h Reset Removal Time t rem Min All Types Typ (Note 6) 5. The formulas given are for the typical characteristics only at 25 C. 6. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance Max Unit mhz s 4

5 PACKAGE DIMENSIONS SOIC6 CASE 75B05 ISSUE K A B P 8 PL 0.25 (0.0) M B S NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0. (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. T SEATING PLANE G D 6 PL K C M R X 45 J F MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G.27 BSC 0 BSC J K M P R (0.0) M T B S A S SOLDERING FOOTPRINT* 8X 6. 6X.2 6 6X PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 5

6 PACKAGE DIMENSIONS SOEIAJ6 CASE 966 ISSUE A e 6 9 Z b D A H E A 0.3 (0.005) M 0. (0.004) 8 E VIEW P M L E Q L DETAIL P c NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0. (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.08). MILLIMETERS INCHES DIM MIN MAX MIN MAX A A b c D E e.27 BSC 0 BSC H E L L E M 0 0 Q Z ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC ow the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any licee under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 27 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC475B/D

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