Sequential Logic Implementation

Transcription

1 Sequential Logic Implementation Models for representing sequential circuits Abstraction of sequential elements Finite state machines and their state diagrams Inputs/outputs Mealy, Moore, and synchronous Mealy machines Finite state machine design procedure Verilog specification eriving state diagram eriving state transition table etermining next state and output functions Implementing combinational logic CS 5 - Fall 25 Lec #7: Sequential Implementation Mealy vs. Moore Machines Moore: outputs dep on current state only Mealy: outputs dep on current state and inputs Ant brain is a Moore Machine Output does not react immediately to input change We could have specified a Mealy FSM Outputs have immediate reaction to inputs As inputs change, so does next state, doesn t commit until clocking event L / TL A L R / TL, F react right away to leaving the wall L R / TR, F CS 5 - Fall 25 Lec #7: Sequential Implementation 2

2 Specifying Outputs for a Moore Machine Output is only function of state Specify in state bubble in state diagram Example: sequence detector for or reset A/ B/ C/ / E/ current next reset input state state output A A B A C B B B C E C C E C E B E CS 5 - Fall 25 Lec #7: Sequential Implementation 3 Specifying Outputs for a Mealy Machine Output is function of state and inputs Specify output on transition arc between states Example: sequence detector for or reset/ / B / A / / / C current next reset input state state output A A B A C B B B C C B C C / CS 5 - Fall 25 Lec #7: Sequential Implementation 4

3 Comparison of Mealy and Moore Machines Mealy Machines t to have less states ifferent outputs on arcs (n^2) rather than states (n) Moore Machines are safer to use Outputs change at clock edge (always one cycle later) In Mealy machines, input change can cause output change as soon as logic is done a big problem when two machines are interconnected asynchronous feedback Mealy Machines react faster to inputs React in same cycle don't need to wait for clock In Moore machines, more logic may be necessary to decode state into outputs more gate delays after inputs Combinational logic for ext State reg Logic for outputs outputs inputs Logic for outputs Combinational logic for ext State reg outputs state feedback CS 5 - Fall 25 Lec #7: Sequential Implementation 5 state feedback Mealy and Moore Examples Recognize A,B =, Mealy or Moore? A B clock out A out B clock CS 5 - Fall 25 Lec #7: Sequential Implementation 6

4 Mealy and Moore Examples (cont d) Recognize A,B =, then, Mealy or Moore? out A B clock out A B clock CS 5 - Fall 25 Lec #7: Sequential Implementation 7 Registered Mealy Machine (Really Moore) Synchronous (or registered) Mealy Machine Registered state A outputs Avoids glitchy outputs Easy to implement in programmable logic Moore Machine with no output decoding Outputs computed on transition to next state rather than after entering View outputs as expanded state vector Inputs output logic next state logic Outputs Current State CS 5 - Fall 25 Lec #7: Sequential Implementation 8

5 Verilog FSM - Reduce s Example Change the first to in each string of s Example Moore machine implementation // State assignment parameter zero =, one =, twos = 2; module reduce (out, clk, reset, in); output out; input clk, reset, in; reg out; reg [:] state; // state register reg [:] next_state; zero [] one [] twos [] CS 5 - Fall 25 Lec #7: Sequential Implementation 9 Moore Verilog FSM (cont d) or state) case (state) zero: begin // last input was a zero out = ; if (in) next_state = one; else next_state = zero; one: begin // we've seen one out = ; if (in) next_state = twos; else next_state = zero; twos: begin // we've seen at least 2 ones out = ; if (in) next_state = twos; else next_state = zero; default: begin // in case we reach a bad state out = ; next_state = zero; case zero [] include all signals that are input to state and output equations one [] twos [] CS 5 - Fall 25 Lec #7: Sequential Implementation

6 Moore Verilog FSM (cont d) // Implement the state register clk) if (reset) state <= zero; else state <= next_state; module zero [] one [] twos [] CS 5 - Fall 25 Lec #7: Sequential Implementation Mealy Verilog FSM for Reduce-s Example module reduce (clk, reset, in, out); input clk, reset, in; output out; reg out; reg state; // state register reg next_state; parameter zero =, one = ; zero / or state) case (state) zero: begin // last input was a zero if (in) next_state = one; else next_state = zero; out = ; one: // we've seen one if (in) begin next_state = one; out = ; else begin next_state = zero; out = ; case / / one / clk) if (reset) state <= zero; else state <= next_state; module CS 5 - Fall 25 Lec #7: Sequential Implementation 2

7 Synchronous Mealy Verilog FSM for Reduce-s Example module reduce (clk, reset, in, out); input clk, reset, in; output out; reg out; reg state; // state register reg next_state; reg next_out; parameter zero =, one = ; or state) case (state) zero: begin // last input was a zero if (in) next_state = one; else next_state = zero; next_out = ; one: // we've seen one if (in) begin next_state = one; next_out = ; else begin next_state = zero; next_out = ; case clk) if (reset) begin state <= zero; out <= ; else begin state <= next_state; out <= next_out; module / CS 5 - Fall 25 Lec #7: Sequential Implementation 3 zero one / / / Announcements Review Session, Today, 5-6 PM, 25 Cory Hall Examination, Wednesday, -2:3 PM, 25 Cory Hall Five uiz-like uestions -- Please Read Them Carefully! They are not inted to be tricky; they should contain all the information you need to answer the question correctly o calculators or other gadgets are necessary! on t bring them! o blue books! All work on the sheets handed out! o bring pencil and eraser please! If you like to unstaple the exam pages, then bring a stapler with you! Write your name and student I on EVERY page in case they get separated -- it has happened! on t forget your two-sided 8.5 x crib sheet! CS 5 - Fall 25 Lec #7: Sequential Implementation 4

8 Announcements Examination, Wednesday, -2:3 PM, 25 Cory Hall Topics covered through last Wednesday Combinational logic: design and optimization (K-maps up to and including 6 variables) Implementation: Simple gates (minimum wires and gates), PLA structures (minimum unique terms), Muxes, ecoders, ROMs, (Simplified) Xilinx CLB Sequential logic: R-S latches, flip-flops, transparent vs. edge-triggered behavior, master/slave concept Basic Finite State Machines: Representations (state diagrams, transition tables), Moore vs. Mealy Machines, Shifters, Registers, Counters Structural and Behavioral Verilog for combinational and sequential logic Labs, 2, 3 K&B: Chapters, 2 (2.-2.5), 3 (3., 3.6), 4 (4., 4.2, 4.3), 6 (6., 6.2., 6.3), 7 (7., 7.2, 7.3) CS 5 - Fall 25 Lec #7: Sequential Implementation 5 Example: Ving Machine Release item after 5 cents are deposited Single coin slot for dimes, nickels o change Reset Coin Sensor Ving Machine FSM Open Release Mechanism Clock CS 5 - Fall 25 Lec #7: Sequential Implementation 6

9 Example: Ving Machine (cont d) Suitable Abstract Representation Tabulate typical input sequences: Reset 3 nickels nickel, dime dime, nickel two dimes S raw state diagram: S S2 Inputs:,, reset Output: open chute Assumptions: S3 S4 [open] S5 [open] S6 [open] Assume and asserted for one cycle Each state has a self loop for = = (no coin) S7 [open] CS 5 - Fall 25 Lec #7: Sequential Implementation 7 Example: Ving Machine (cont d) Minimize number of states - reuse states whenever possible 5 Reset + present inputs next output state state open [open] symbolic state table CS 5 - Fall 25 Lec #7: Sequential Implementation 8

10 Example: Ving Machine (cont d) Uniquely Encode States present state inputs next state output open CS 5 - Fall 25 Lec #7: Sequential Implementation 9 Example: Ving Machine (cont d) Mapping to Logic X X X X X X X X Open X X X X = + + = OPE = CS 5 - Fall 25 Lec #7: Sequential Implementation 2

11 Example: Ving Machine (cont d) One-hot Encoding present state inputs next state output open = = + 2 = = OPE = 3 CS 5 - Fall 25 Lec #7: Sequential Implementation 2 Equivalent Mealy and Moore State iagrams Moore machine outputs associated with state Mealy machine outputs associated with transitions Reset + Reset Reset/ ( + Reset)/ [] / / 5 [] / 5 / / [] / / + +/ 5 [] Reset 5 Reset / CS 5 - Fall 25 Lec #7: Sequential Implementation 22

12 Moore Verilog FSM for Ving Machine module ving (open, Clk, Reset,, ); input Clk, Reset,, ; output open; reg open; reg state; // state register reg next_state; parameter zero =, five =, ten = 2, fifteen = 3; or or state) case (state) zero: begin if () next_state = five; else if () next_state = ten; case else open = ; fifteen: begin next_state = zero; if (!Reset) next_state = fifteen; else next_state = zero; open = ; clk) if (Reset (! &&!)) state <= zero; else state <= next_state; module Reset [] + 5 [] [] 5 [] + Reset Reset CS 5 - Fall 25 Lec #7: Sequential Implementation 23 Mealy Verilog FSM for Ving Machine module ving (open, Clk, Reset,, ); input Clk, Reset,, ; output open; reg open; reg state; // state register reg next_state; reg next_open; parameter zero =, five =, ten = 2, fifteen = 3; or or state) case (state) zero: begin if () begin next_state = ten; next_open = ; else if () begin next_state = five; next_open = ; else begin next_state = zero; next_open = ; case Reset/ ( + Reset)/ / / / 5 / / / / +/ 5 Reset / clk) if (Reset (! &&!)) begin state <= zero; open <= ; else begin state <= next_state; open <= next_open; module CS 5 - Fall 25 Lec #7: Sequential Implementation 24

13 Example: Traffic Light Controller A busy highway is intersected by a little used farmroad etectors C sense the presence of cars waiting on the farmroad with no car on farmroad, light remain green in highway direction if vehicle on farmroad, highway lights go from Green to Yellow to Red, allowing the farmroad lights to become green these stay green only as long as a farmroad car is detected but never longer than a set interval when these are met, farm lights transition from Green to Yellow to Red, allowing highway to return to green even if farmroad vehicles are waiting, highway gets at least a set interval as green Assume you have an interval timer that generates: a short time pulse (TS) and a long time pulse (TL), in response to a set (ST) signal. TS is to be used for timing yellow lights and TL for green lights CS 5 - Fall 25 Lec #7: Sequential Implementation 25 Example: Traffic Light Controller (cont d) Highway/farm road intersection farm road car sensors highway CS 5 - Fall 25 Lec #7: Sequential Implementation 26

14 Example: Traffic Light Controller (cont d) Tabulation of Inputs and Outputs inputs description outputs description reset place FSM in initial state HG, HY, HR assert green/yellow/red highway lights C detect vehicle on the farm road FG, FY, FR assert green/yellow/red highway lights TS short time interval expired ST start timing a short or long interval TL long time interval expired Tabulation of unique states some light configurations imply others state description S highway green (farm road red) S highway yellow (farm road red) S2 farm road green (highway red) S3 farm road yellow (highway red) CS 5 - Fall 25 Lec #7: Sequential Implementation 27 Example: Traffic Light Controller (cont d) State iagram (TL C)' Reset S S: HG S: HY TS' TL C / ST TL+C / ST S TS / ST S3 TS' S2: FG S3: FY TS / ST S2 TL+C' / ST (TL+C')' CS 5 - Fall 25 Lec #7: Sequential Implementation 28

15 Example: Traffic Light Controller (cont d) Generate state table with symbolic states Consider state assignments output encoding similar problem to state assignment (Green =, Yellow =, Red = ) Inputs Present State ext State Outputs C TL TS ST H F HG HG Green Red HG HG Green Red HG HY Green Red HY HY Yellow Red HY FG Yellow Red FG FG Red Green FG FY Red Green FG FY Red Green FY FY Red Yellow FY HG Red Yellow SA: HG = HY = FG = FY = SA2: HG = HY = FG = FY = SA3: HG = HY = FG = FY = (one-hot) CS 5 - Fall 25 Lec #7: Sequential Implementation 29 Traffic Light Controller Verilog module traffic (ST, Clk, Reset, C, TL, TS); input Clk, Reset, C, TL, TS; output ST; reg ST; reg state; reg next_state; reg next_st; parameter S =, S =, S2 = 2, S3 = 3; or TL or TS or state) case (state) S: if (!(TL && C)) begin next_state = S; next_st = ; else if (TL C) begin next_state = S; next_st = ; case TS' (TL C)' Reset S TL C TS / ST TL+C / ST S S3 TS / ST TL+C' / ST S2 TS' Clk) if (Reset) begin state <= S; ST <= ; else begin state <= next_state; ST <= next_st; module (TL+C')' CS 5 - Fall 25 Lec #7: Sequential Implementation 3

16 Logic for ifferent State Assignments SA S = C TL' PS PS + TS PS' PS + TS PS PS' + C' PS PS + TL PS PS S = C TL PS' PS' + C TL' PS PS + PS' PS ST = C TL PS' PS' + TS PS' PS + TS PS PS' + C' PS PS + TL PS PS H = PS H = PS' PS F = PS' F = PS PS' SA2 S = C TL PS' + TS' PS + C' PS' PS S = TS PS PS' + PS' PS + TS' PS PS SA3 ST = C TL PS' + C' PS' PS + TS PS H = PS H = PS PS' F = PS' F = PS PS S3 = C' PS2 + TL PS2 + TS' PS3 S2 = TS PS + C TL' PS2 S = C TL PS + TS' PS S = C' PS + TL' PS + TS PS3 ST = C TL PS + TS PS + C' PS2 + TL PS2 + TS PS3 H = PS3 + PS2 H = PS F = PS + PS F = PS3 CS 5 - Fall 25 Lec #7: Sequential Implementation 3 Ving Machine Example Revisted (PL mapping) OPE = reset'(' + ' + + ) = reset'( + + ) = CLK Seq Seq Open Reset Com CS 5 - Fall 25 Lec #7: Sequential Implementation 32

17 Ving Machine (cont d) OPE = creates a combinational delay after and change This can be corrected by retiming, i.e., move flip-flops and logic through each other to improve delay OPE = reset'( + + )(' + ' + + ) = reset'(' ' + ') Implementation now looks like a synchronous Mealy machine Common for programmable devices to have FF at of logic CS 5 - Fall 25 Lec #7: Sequential Implementation 33 Ving Machine (Retimed PL Mapping) OPE = reset'(' ' + ') CLK Seq Seq OPE Open Reset Seq CS 5 - Fall 25 Lec #7: Sequential Implementation 34

18 Sequential Logic Implementation Summary Models for representing sequential circuits Abstraction of sequential elements Finite state machines and their state diagrams Inputs/outputs Mealy, Moore, and synchronous Mealy machines Finite state machine design procedure Verilog specification eriving state diagram eriving state transition table etermining next state and output functions Implementing combinational logic CS 5 - Fall 25 Lec #7: Sequential Implementation 35