RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition"

Transcription

1 RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition A Tutorial Approach James O. Hamblen Georgia Institute of Technology Michael D. Furman Georgia Institute of Technology KLUWER ACADEMIC PUBLISHERS Boston / Dordrecht / London

2 RAPID PROTOTYPING OF DIGITAL SYSTEMS SECOND Table of Contents EDITION 1 Tutorial I: The 15 Minute Design 1.1 Design Entry using the Graphic Editor 1.2 Compiling the Design 1.3 Simulation of the Design 1.4 Downloading Your Design to the UP 1 or UP IX Board 1.5 The 10 Minute VHDL Entry Tutorial 1.6 Compiling the VHDL Design 1.7 The 10 Minute Verilog Entry Tutorial 1.8 Compiling the Verilog Design 1.9 Timing Analysis 1.10 The Floorplan Editor 1.11 Symbols and Hierarchy 1.12 Functional Simulation 1.13 For additional Information 1.14 Laboratory Exercises 2 The Altera UP 1 and UP IX CPLD Boards_ 2.1 Programming Jumpers 2.2 MAX 7000 Device and UP 1 I/O Features 2.3 MAX and FLEX Seven-segment LED Displays, 2.4 FLEX 10K Device and UP 1 I/O Features 2.5 Obtaining a UP 1 or UP IX Board and Power Supply 3 Programmahle Logic Technology 3.1 CPLDs and FPGAs 3.2 Altera MAX 7000S Architecture - A Product Term CPLD Device_ 3.3 Altera FLEX 10K Architecture - A Look-Up Table CPLD Device_ 3.4 Xilinx 4000 Architecture - A Look-Up Table FPGA Device

3 vi Rapid Prototyping of Digital Systems 3.5 Computer Aided Design Tools for Programmable Logic 3.6 Next Generation FPLD CAD tools 3.7 Applications offplds 3.8 Features of New Generation FPLDs 3.9 For additional information 3.10 Laboratory Exercises 4 Tutorial II: Sequential Design and Hierarchy_ 4.1 Install the Tutorial Files and UPlcore Library 4.2 Open the tutor2 Schematic 4.3 Browse the Hierarchy 4.4 Using Buses in a Schematic 4.5 Testing the Pushbutton Counter and Displays 4.6 Testing the Initial Design on the UP 1 Board._ 4.7 Fixing the Switch Contact Bounce Problem 4.8 Testing the Modified Design on the UP 1 Board. 4.9 Laboratory Exercises 5 UPlcore Library Functions 5.1 UPlcore DEC_7SEG: Hex to Seven-segment Decoder 5.2 UPlcore Debounce: Pushbutton Debounce 5.3 UPlcore OnePulse: Pushbutton Single Pulse_ 5.4 UPlcore Clk Div: Clock Divider 5.5 UPlcore VGASync: VGA Video Sync Generation, 5.6 UPlcore CHAR ROM: Character Generation ROM 5.7 UPlcore Keyboard: Read Keyboard Scan Code 5.8 UPlcore Mouse: Mouse Cursor 6 Using VHDL for Synthesis of Digital Hardware 6.1 VHDL Data Types 6.2 VHDL Operators 6.3 VHDL Based Synthesis of Digital Hardware 6.4 VHDL Synthesis Models of Gate Networks _ 6.5 VHDL Synthesis Model of a Seven-segment LED Decoder 6.6 VHDL Synthesis Model of a Multiplexer 6.7 VHDL Synthesis Model of Tri-State Output

4 vi Rapid Prototyping of Digital Systems 3.5 Computer Aided Design Tools for Programmable Logic Next Generation FPLD CAD tools Applications offplds Features of New Generation FPLDs For additional information Laboratory Exercises 52 4 Tutorial II: Sequential Design and Hierarchy Install the Tutorial Files and UPlcore Library Open the tutor2 Schematic Browse the Hierarchy Using Buses in a Schematic Testing the Pushbutton Counter and Displays Testing the Initial Design on the UP 1 Board Fixing the Switch Contact Bounce Problem Testing the Modified Design on the UP 1 Board Laboratory Exercises 61 5 UPlcore Library Functions UPlcore DEC_7SEG: Hex to Seven-segment Decoder UPlcore Debounce: Pushbutton Debounce UPlcore OnePulse: Pushbutton Single Pulse UPlcore Clk_Div: Clock Divider UPlcore VGASync: VGA Video Sync Generation UPlcore CHAR ROM: Character Generation ROM UPlcore Keyboard: Read Keyboard Scan Code UPlcore Mouse: Mouse Cursor 75 6 Using VHDL for Synthesis of Digital Hardware VHDL Data Types VHDL Operators VHDL Based Synthesis of Digital Hardware VHDL Synthesis Models of Gate Networks VHDL Synthesis Model of a Seven-segment LED Decoder VHDL Synthesis Model of a Multiplexer VHDL Synthesis Model of Tri-State Output 84

5 Table of Contents VII 6.8 VHDL Synthesis Models of Flip-flops and Registers Accidental Synthesis of Inferred Latches VHDL Synthesis Model of a Counter VHDL Synthesis Model of a State Machine VHDL Synthesis Model of an ALU with an Adder/Subtractor and a Shifter VHDL Synthesis of Multiply and Divide Hardware VHDL Synthesis Models for Memory Hierarchy in VHDL Synthesis Models Using a Testbench for Verification For additional information Laboratory Exercises 97 7 State Machine Design: The Electric Train Controller The Train Control Problem Track Power (Tl, T2, T3, and T4) Track Direction (DA1-DA0, and DB1-DB0) Switch Direction (SW1, SW2, and SW3) Train Sensor Input Signals (Sl, S2, S3, S4, and S5) An Example Controller Design VHDL Based Example Controller Design Simulation Vector file for State Machine Simulation Running the Train Control Simulation Running the Video Train System (After SuccessfuI Simulation) Laboratory Exercises A Simple Computer Design: The /JP Computer Programs and Instructions The Processor Fetch, Decode and Execute Cycle VHDL Model of the np Simulation of the npl Computer Laboratory Exercises VGA Video Display Generation Video Display Technology Video Refresh Using a CPLD for VGA Video Signal Generation 143

6 VIII Rapid Prototyping of Digital Systems 9.4 A VHDL Sync Generation Example: UPlcore VGA SYNC Final Output Register for Video Signals Required Pin Assignments for Video Output Video Examples A Character Based Video Design Character Selection and Fonts VHDL Character Display Design Examples A Graphics Memory Design Example Video Data Compression Video Color Mixing using Dithering VHDL Graphics Display Design Example Laboratory Exercises Communications: Interfacing to the PS/2 Keyboard PS/2 Port Connections Keyboard Scan Codes Make and Break Codes The PS/2 Serial Data Transmission Protocol Scan Code Set 2 for the PS/2 Keyboard The Keyboard UPlcore A Design Example Using the Keyboard UPlcore For Additional Information Laboratory Exercises Communications: Interfacing to the PS/2 Mouse The Mouse UPlcore Mouse Initialization Mouse Data Packet Processing An Example Design Using the Mouse UPlcore For Additional Information Laboratory Exercises Robotics: The UPI-bot The UPl-bot Design UPl-bot Servo Drive Motors Modifying the Servos to make Drive Motors 179

7 Table of Contents ix 12.4 VHDL Servo Driver Code for the UPl-bot 12.5 Sensors for the UPl-bot 12.6 Assembly of the UPl-bot Body 12.7 UPl-bot FLEX Expansion B Header Pins 12.8 An Alternative UP 1 Robot Pro.ject Based on an R/C Car 12.9 For Additional Information Laboratory Exercises 13 A RISC Design: Synthesis ofthe MIPS Processor Core 13.1 The MIPS Instruction Set and Processor 13.2 Using VHDL to Synthesize the MIPS Processor Core 13.3 The Top-Level Module 13.4 The Control Unit 13.5 The Instruction Fetch Stage 13.6 The Decode Stage 13.7 The Execute Stage 13.8 The Data Memory Stage 13.9 Simulation of the MIPS Design MIPS Hardware Implementation on the UP 1 or UP IX Board For Additional Information Laboratory Exercises Appendix A: Generation ofpseudo Random Binary Sequences Appendix B: MAX+PLUS II Design and Data File Extensions Appendix C: UP 1 and UP IX Pin Assignments Appendix D: The Wintim Meta Assembler Appendix E: An Introduction to Verilog for VHDL users Glossarv Index About the Accompanying CD-ROM

Rapid System Prototyping with FPGAs

Rapid System Prototyping with FPGAs Rapid System Prototyping with FPGAs By R.C. Coferand Benjamin F. Harding AMSTERDAM BOSTON HEIDELBERG LONDON NEW YORK OXFORD PARIS SAN DIEGO SAN FRANCISCO SINGAPORE SYDNEY TOKYO Newnes is an imprint of

More information

Digitale Signalverarbeitung mit FPGA (DSF) Soft Core Prozessor NIOS II Stand Mai 2007. Jens Onno Krah

Digitale Signalverarbeitung mit FPGA (DSF) Soft Core Prozessor NIOS II Stand Mai 2007. Jens Onno Krah (DSF) Soft Core Prozessor NIOS II Stand Mai 2007 Jens Onno Krah Cologne University of Applied Sciences www.fh-koeln.de jens_onno.krah@fh-koeln.de NIOS II 1 1 What is Nios II? Altera s Second Generation

More information

FPGA Development Board Hardware and I/O Features

FPGA Development Board Hardware and I/O Features CHAPTER 2 FPGA Development Board Hardware and I/O Features Photo: The Altera DE1 board contains a Cyclone II FPGA, external SRAM, SDRAM & Flash memory, and a wide assortment of I/O devices and connectors.

More information

Introduction to Programmable Logic Controllers (PLC's)

Introduction to Programmable Logic Controllers (PLC's) NDSU Intro to PLC's 1 Introduction to Programmable Logic Controllers (PLC's) Programmable Logic Controllers (PLC's) are microprocessor devices much like the PIC microcontroller. Their function is to control

More information

University of St. Thomas ENGR 230 ---- Digital Design 4 Credit Course Monday, Wednesday, Friday from 1:35 p.m. to 2:40 p.m. Lecture: Room OWS LL54

University of St. Thomas ENGR 230 ---- Digital Design 4 Credit Course Monday, Wednesday, Friday from 1:35 p.m. to 2:40 p.m. Lecture: Room OWS LL54 Fall 2005 Instructor Texts University of St. Thomas ENGR 230 ---- Digital Design 4 Credit Course Monday, Wednesday, Friday from 1:35 p.m. to 2:40 p.m. Lecture: Room OWS LL54 Lab: Section 1: OSS LL14 Tuesday

More information

Lab #5: Design Example: Keypad Scanner and Encoder - Part 1 (120 pts)

Lab #5: Design Example: Keypad Scanner and Encoder - Part 1 (120 pts) Dr. Greg Tumbush, gtumbush@uccs.edu Lab #5: Design Example: Keypad Scanner and Encoder - Part 1 (120 pts) Objective The objective of lab assignments 5 through 9 are to systematically design and implement

More information

Implementation of Web-Server Using Altera DE2-70 FPGA Development Kit

Implementation of Web-Server Using Altera DE2-70 FPGA Development Kit 1 Implementation of Web-Server Using Altera DE2-70 FPGA Development Kit A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENT OF FOR THE DEGREE IN Bachelor of Technology In Electronics and Communication

More information

Quartus II Software Design Series : Foundation. Digitale Signalverarbeitung mit FPGA. Digitale Signalverarbeitung mit FPGA (DSF) Quartus II 1

Quartus II Software Design Series : Foundation. Digitale Signalverarbeitung mit FPGA. Digitale Signalverarbeitung mit FPGA (DSF) Quartus II 1 (DSF) Quartus II Stand: Mai 2007 Jens Onno Krah Cologne University of Applied Sciences www.fh-koeln.de jens_onno.krah@fh-koeln.de Quartus II 1 Quartus II Software Design Series : Foundation 2007 Altera

More information

Fast and Effective Embedded Systems Design

Fast and Effective Embedded Systems Design Fast and Effective Embedded Systems Design Applying the ARM mbed Rob Toulson Tim Wilmshurst AMSTERDAM BOSTON HEIDELBERG LONDON NEW YORK OXFORD чч*?? &Ш& PARIS SAN DIEGO SAN FRANCISCO SINGAPORE SYDNEY TOKYO

More information

Efficient Teaching of Digital Design with Automated Assessment and Feedback

Efficient Teaching of Digital Design with Automated Assessment and Feedback Efficient Teaching of Digital Design with Automated Assessment and Feedback 1 Paul W. Nutter, Member, IEEE, 2 Vasilis F. Pavlidis, Member, IEEE, and 2 Jeffrey Pepper 1 Nano Engineering and Storage Technology

More information

A First Course in Digital Design Using VHDL and Programmable Logic

A First Course in Digital Design Using VHDL and Programmable Logic A First Course in Digital Design Using VHDL and Programmable Logic Shawki Areibi Abstract Present industry practice has created a high demand for systems designers with knowledge and experience in using

More information

Verilog Combinational Logic. Verilog for Synthesis

Verilog Combinational Logic. Verilog for Synthesis Verilog Combinational Logic Verilog for Synthesis 1 Verilog logic and numbers Four-value logic system 0 logic zero, or false condition 1 logic 1, or true condition x, X unknown logic value z, Z - high-impedance

More information

Technical Aspects of Creating and Assessing a Learning Environment in Digital Electronics for High School Students

Technical Aspects of Creating and Assessing a Learning Environment in Digital Electronics for High School Students Session: 2220 Technical Aspects of Creating and Assessing a Learning Environment in Digital Electronics for High School Students Adam S. El-Mansouri, Herbert L. Hess, Kevin M. Buck, Timothy Ewers Microelectronics

More information

Chapter 2 Logic Gates and Introduction to Computer Architecture

Chapter 2 Logic Gates and Introduction to Computer Architecture Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are

More information

Lab 1: Introduction to Xilinx ISE Tutorial

Lab 1: Introduction to Xilinx ISE Tutorial Lab 1: Introduction to Xilinx ISE Tutorial This tutorial will introduce the reader to the Xilinx ISE software. Stepby-step instructions will be given to guide the reader through generating a project, creating

More information

Laboratory Exercise 3

Laboratory Exercise 3 Laboratory Exercise 3 Latches, Flip-flops, and egisters The purpose of this exercise is to investigate latches, flip-flops, and registers. Part I Altera FPGAs include flip-flops that are available for

More information

SKP16C62P Tutorial 1 Software Development Process using HEW. Renesas Technology America Inc.

SKP16C62P Tutorial 1 Software Development Process using HEW. Renesas Technology America Inc. SKP16C62P Tutorial 1 Software Development Process using HEW Renesas Technology America Inc. 1 Overview The following tutorial is a brief introduction on how to develop and debug programs using HEW (Highperformance

More information

Embedded Software development Process and Tools: Lesson-4 Linking and Locating Software

Embedded Software development Process and Tools: Lesson-4 Linking and Locating Software Embedded Software development Process and Tools: Lesson-4 Linking and Locating Software 1 1. Linker 2 Linker Links the compiled codes of application software, object codes from library and OS kernel functions.

More information

Introduction to Digital Design Using Digilent FPGA Boards Block Diagram / Verilog Examples

Introduction to Digital Design Using Digilent FPGA Boards Block Diagram / Verilog Examples Introduction to Digital Design Using Digilent FPGA Boards Block Diagram / Verilog Examples Richard E. Haskell Darrin M. Hanna Oakland University, Rochester, Michigan LBE Books Rochester Hills, MI Copyright

More information

Aims and Objectives. E 3.05 Digital System Design. Course Syllabus. Course Syllabus (1) Programmable Logic

Aims and Objectives. E 3.05 Digital System Design. Course Syllabus. Course Syllabus (1) Programmable Logic Aims and Objectives E 3.05 Digital System Design Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk How to go

More information

EXPERIMENT 8. Flip-Flops and Sequential Circuits

EXPERIMENT 8. Flip-Flops and Sequential Circuits EXPERIMENT 8. Flip-Flops and Sequential Circuits I. Introduction I.a. Objectives The objective of this experiment is to become familiar with the basic operational principles of flip-flops and counters.

More information

An Introductory Digital Design Course Using a Low-Cost Autonomous Robot

An Introductory Digital Design Course Using a Low-Cost Autonomous Robot IEEE TRANSACTIONS ON EDUCATION, VOL. 45, NO. 3, AUGUST 2002 289 An Introductory Digital Design Course Using a Low-Cost Autonomous Robot Kimberly E. Newman, Member, IEEE, James O. Hamblen, Senior Member,

More information

Modeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit

Modeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit Modeling Sequential Elements with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 4-1 Sequential Circuit Outputs are functions of inputs and present states of storage elements

More information

Black Box for Robot Manipulation

Black Box for Robot Manipulation Black Box for Robot Manipulation Second Prize Black Box for Robot Manipulation Institution: Participants: Hanyang University, Seoul National University, Yonsei University Kim Hyong Jun, Ahn Ho Seok, Baek

More information

Modeling Registers and Counters

Modeling Registers and Counters Lab Workbook Introduction When several flip-flops are grouped together, with a common clock, to hold related information the resulting circuit is called a register. Just like flip-flops, registers may

More information

A Practical One-Semester VLSI Design Course for Computer Science (and Other) Majors

A Practical One-Semester VLSI Design Course for Computer Science (and Other) Majors A Practical One-Semester VLSI Design Course for Computer Science (and Other) Majors Robert A. Walker Kent State University Department of Math and Computer Science Kent, OH 44242 walker@mcs.kent.edu Abstract

More information

Digital Systems Design! Lecture 1 - Introduction!!

Digital Systems Design! Lecture 1 - Introduction!! ECE 3401! Digital Systems Design! Lecture 1 - Introduction!! Course Basics Classes: Tu/Th 11-12:15, ITE 127 Instructor Mohammad Tehranipoor Office hours: T 1-2pm, or upon appointments @ ITE 441 Email:

More information

Computer Organization and Components

Computer Organization and Components Computer Organization and Components IS1500, fall 2015 Lecture 5: I/O Systems, part I Associate Professor, KTH Royal Institute of Technology Assistant Research Engineer, University of California, Berkeley

More information

Ping Pong Game with Touch-screen. March 2012

Ping Pong Game with Touch-screen. March 2012 Ping Pong Game with Touch-screen March 2012 xz2266 Xiang Zhou hz2256 Hao Zheng rz2228 Ran Zheng yc2704 Younggyun Cho Abstract: This project is conducted using the Altera DE2 development board. We are aiming

More information

Quartus II Introduction for VHDL Users

Quartus II Introduction for VHDL Users Quartus II Introduction for VHDL Users This tutorial presents an introduction to the Quartus II software. It gives a general overview of a typical CAD flow for designing circuits that are implemented by

More information

Digital System Design. Digital System Design with Verilog

Digital System Design. Digital System Design with Verilog Digital System Design with Verilog Adapted from Z. Navabi Portions Copyright Z. Navabi, 2006 1 Digital System Design Automation with Verilog Digital Design Flow Design entry Testbench in Verilog Design

More information

UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering. EEC180B Lab 7: MISP Processor Design Spring 1995

UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering. EEC180B Lab 7: MISP Processor Design Spring 1995 UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering EEC180B Lab 7: MISP Processor Design Spring 1995 Objective: In this lab, you will complete the design of the MISP processor,

More information

AC 2007-2485: PRACTICAL DESIGN PROJECTS UTILIZING COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLD)

AC 2007-2485: PRACTICAL DESIGN PROJECTS UTILIZING COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLD) AC 2007-2485: PRACTICAL DESIGN PROJECTS UTILIZING COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLD) Samuel Lakeou, University of the District of Columbia Samuel Lakeou received a BSEE (1974) and a MSEE (1976)

More information

Modeling Latches and Flip-flops

Modeling Latches and Flip-flops Lab Workbook Introduction Sequential circuits are digital circuits in which the output depends not only on the present input (like combinatorial circuits), but also on the past sequence of inputs. In effect,

More information

EC313 - VHDL State Machine Example

EC313 - VHDL State Machine Example EC313 - VHDL State Machine Example One of the best ways to learn how to code is seeing a working example. Below is an example of a Roulette Table Wheel. Essentially Roulette is a game that selects a random

More information

Modeling Registers and Counters

Modeling Registers and Counters Lab Workbook Introduction When several flip-flops are grouped together with a common clock to hold related information, the resulting circuit is called a register. Just like flip-flops, registers may also

More information

Modeling Latches and Flip-flops

Modeling Latches and Flip-flops Introduction Sequential circuits are the digital circuits in which the output deps not only on the present input (like combinatorial circuits), but also on the past sequence of inputs. In effect, these

More information

Experiment 20 D Latches and D Flip-flops

Experiment 20 D Latches and D Flip-flops Objectives Experiment 20 D Latches and D Flip-flops Upon completion of this laboratory exercise, you should be able to: Create multiple-bit latches and flip-flops in VHDL. Create simulations for the latches

More information

USB-CPLD DEVELOPMENT SYSTEM FOR THE ARDUINO

USB-CPLD DEVELOPMENT SYSTEM FOR THE ARDUINO USB-CPLD DEVELOPMENT SYSTEM FOR THE ARDUINO The EPT USB-CPLD development system provides an innovative method of developing and debugging programmable logic code. It also provides a high speed data transfer

More information

LiveDesign Evaluation Board Technical Reference Manual. Technical reference manual for Altium s LiveDesign Evaluation Boards

LiveDesign Evaluation Board Technical Reference Manual. Technical reference manual for Altium s LiveDesign Evaluation Boards LiveDesign Evaluation Board Technical Reference Manual Technical reference manual for Altium s LiveDesign Evaluation Boards CAUTION THIS EQUIPMENT INCLUDES EXPOSED ELECTRONIC COMPONENTS THAT ARE HIGHLY

More information

Simulation & Synthesis Using VHDL

Simulation & Synthesis Using VHDL Floating Point Multipliers: Simulation & Synthesis Using VHDL By: Raj Kumar Singh - B.E. (Hons.) Electrical & Electronics Shivananda Reddy - B.E. (Hons.) Electrical & Electronics BITS, PILANI Outline Introduction

More information

Quartus II Introduction Using Schematic Design

Quartus II Introduction Using Schematic Design Quartus II Introduction Using Schematic Design This tutorial presents an introduction to the Quartus R II CAD system. It gives a general overview of a typical CAD flow for designing circuits that are implemented

More information

Introduction to the Altera Qsys System Integration Tool. 1 Introduction. For Quartus II 12.0

Introduction to the Altera Qsys System Integration Tool. 1 Introduction. For Quartus II 12.0 Introduction to the Altera Qsys System Integration Tool For Quartus II 12.0 1 Introduction This tutorial presents an introduction to Altera s Qsys system inegration tool, which is used to design digital

More information

Digital Circuit Design Using Xilinx ISE Tools

Digital Circuit Design Using Xilinx ISE Tools Digital Circuit Design Using Xilinx ISE Tools Contents 1. Introduction... 1 2. Programmable Logic Device: FPGA... 2 3. Creating a New Project... 2 4. Synthesis and Implementation of the Design... 11 5.

More information

8051 MICROCONTROLLER COURSE

8051 MICROCONTROLLER COURSE 8051 MICROCONTROLLER COURSE Objective: 1. Familiarization with different types of Microcontroller 2. To know 8051 microcontroller in detail 3. Programming and Interfacing 8051 microcontroller Prerequisites:

More information

MAX+PLUS II. Introduction. Programmable Logic Development System & Software

MAX+PLUS II. Introduction. Programmable Logic Development System & Software MAX+PLUS II Programmable Logic Development System & Software January 1998, ver. 8 Data Sheet Introduction Ideally, a programmable logic design environment satisfies a large variety of design requirements:

More information

E158 Intro to CMOS VLSI Design. Alarm Clock

E158 Intro to CMOS VLSI Design. Alarm Clock E158 Intro to CMOS VLSI Design Alarm Clock Sarah Yi & Samuel (Tae) Lee 4/19/2010 Introduction The Alarm Clock chip includes the basic functions of an alarm clock such as a running clock time and alarm

More information

Digital Systems Design. VGA Video Display Generation

Digital Systems Design. VGA Video Display Generation Digital Systems Design Video Signal Generation for the Altera DE Board Dr. D. J. Jackson Lecture 12-1 VGA Video Display Generation A VGA signal contains 5 active signals Two TTL compatible signals for

More information

DDS. 16-bit Direct Digital Synthesizer / Periodic waveform generator Rev. 1.4. Key Design Features. Block Diagram. Generic Parameters.

DDS. 16-bit Direct Digital Synthesizer / Periodic waveform generator Rev. 1.4. Key Design Features. Block Diagram. Generic Parameters. Key Design Features Block Diagram Synthesizable, technology independent VHDL IP Core 16-bit signed output samples 32-bit phase accumulator (tuning word) 32-bit phase shift feature Phase resolution of 2π/2

More information

Laboratory Exercise 3

Laboratory Exercise 3 Laboratory Exercise 3 Latches, Flip-flops, and egisters The purpose of this exercise is to investigate latches, flip-flops, and registers. Part I Altera FPGAs include flip-flops that are available for

More information

Using Xilinx ISE for VHDL Based Design

Using Xilinx ISE for VHDL Based Design ECE 561 Project 4-1 - Using Xilinx ISE for VHDL Based Design In this project you will learn to create a design module from VHDL code. With Xilinx ISE, you can easily create modules from VHDL code using

More information

Learning Digital Systems Design in VHDL by Example in a Junior Course

Learning Digital Systems Design in VHDL by Example in a Junior Course Learning Digital Systems Design in VHDL by Example in a Junior Course Darrin M. Hanna and Richard E. Haskell School of Engineering and Computer Science Oakland University dmhanna@oakland.edu haskell@oakland.edu

More information

Chapter 6. Inside the System Unit. What You Will Learn... Computers Are Your Future. What You Will Learn... Describing Hardware Performance

Chapter 6. Inside the System Unit. What You Will Learn... Computers Are Your Future. What You Will Learn... Describing Hardware Performance What You Will Learn... Computers Are Your Future Chapter 6 Understand how computers represent data Understand the measurements used to describe data transfer rates and data storage capacity List the components

More information

Below is a diagram explaining the data packet and the timing related to the mouse clock while receiving a byte from the PS-2 mouse:

Below is a diagram explaining the data packet and the timing related to the mouse clock while receiving a byte from the PS-2 mouse: PS-2 Mouse: The Protocol: For out mini project we designed a serial port transmitter receiver, which uses the Baud rate protocol. The PS-2 port is similar to the serial port (performs the function of transmitting

More information

INTRODUCTION TO DIGITAL SYSTEMS. IMPLEMENTATION: MODULES (ICs) AND NETWORKS IMPLEMENTATION OF ALGORITHMS IN HARDWARE

INTRODUCTION TO DIGITAL SYSTEMS. IMPLEMENTATION: MODULES (ICs) AND NETWORKS IMPLEMENTATION OF ALGORITHMS IN HARDWARE INTRODUCTION TO DIGITAL SYSTEMS 1 DESCRIPTION AND DESIGN OF DIGITAL SYSTEMS FORMAL BASIS: SWITCHING ALGEBRA IMPLEMENTATION: MODULES (ICs) AND NETWORKS IMPLEMENTATION OF ALGORITHMS IN HARDWARE COURSE EMPHASIS:

More information

What are embedded systems? Challenges in embedded computing system design. Design methodologies.

What are embedded systems? Challenges in embedded computing system design. Design methodologies. Embedded Systems Sandip Kundu 1 ECE 354 Lecture 1 The Big Picture What are embedded systems? Challenges in embedded computing system design. Design methodologies. Sophisticated functionality. Real-time

More information

Von der Hardware zur Software in FPGAs mit Embedded Prozessoren. Alexander Hahn Senior Field Application Engineer Lattice Semiconductor

Von der Hardware zur Software in FPGAs mit Embedded Prozessoren. Alexander Hahn Senior Field Application Engineer Lattice Semiconductor Von der Hardware zur Software in FPGAs mit Embedded Prozessoren Alexander Hahn Senior Field Application Engineer Lattice Semiconductor AGENDA Overview Mico32 Embedded Processor Development Tool Chain HW/SW

More information

EMBEDDED SYSTEMS DESIGN DECEMBER 2012

EMBEDDED SYSTEMS DESIGN DECEMBER 2012 Q.2a. List and define the three main characteristics of embedded systems that distinguish such systems from other computing systems. Draw and explain the simplified revenue model for computing revenue

More information

Active Learning in the Introduction to Digital Logic Design Laboratory Course

Active Learning in the Introduction to Digital Logic Design Laboratory Course Active Learning in the Introduction to Digital Logic Design Laboratory Course Jing Pang Department of Electrical and Electronic Engineering, Computer Engineering Program, California State University, Sacramento,

More information

Logical Operations. Control Unit. Contents. Arithmetic Operations. Objectives. The Central Processing Unit: Arithmetic / Logic Unit.

Logical Operations. Control Unit. Contents. Arithmetic Operations. Objectives. The Central Processing Unit: Arithmetic / Logic Unit. Objectives The Central Processing Unit: What Goes on Inside the Computer Chapter 4 Identify the components of the central processing unit and how they work together and interact with memory Describe how

More information

MICROPROCESSOR. Exclusive for IACE Students www.iace.co.in iacehyd.blogspot.in Ph: 9700077455/422 Page 1

MICROPROCESSOR. Exclusive for IACE Students www.iace.co.in iacehyd.blogspot.in Ph: 9700077455/422 Page 1 MICROPROCESSOR A microprocessor incorporates the functions of a computer s central processing unit (CPU) on a single Integrated (IC), or at most a few integrated circuit. It is a multipurpose, programmable

More information

HC(S)08-System for Development and Training

HC(S)08-System for Development and Training SYSTECH J.Schnyder GmbH Schliefweg 30 CH-4106 Therwil Telefon 091 827 15 87 www.systech.ch HC(S)08-System for Development and Training Overview V 0.3 (Draft English) Contents Components... 3 Hardware...

More information

Digital Systems. Role of the Digital Engineer

Digital Systems. Role of the Digital Engineer Digital Systems Role of the Digital Engineer Digital Design Engineers attempt to clearly define the problem(s) Possibly, break the problem into many smaller problems Engineers then develop a strategy for

More information

Introducción. Diseño de sistemas digitales.1

Introducción. Diseño de sistemas digitales.1 Introducción Adapted from: Mary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg431 [Original from Computer Organization and Design, Patterson & Hennessy, 2005, UCB] Diseño de sistemas digitales.1

More information

COMPILER PROCESSING During your early design stages, use Functional Compilation and Simulation to design the finite state machine.

COMPILER PROCESSING During your early design stages, use Functional Compilation and Simulation to design the finite state machine. Page 1/9 Revision 1 8-Nov-06 PURPOSE The purpose of this lab is to produce the complete glass typewriter. To accomplish this task will require three subtasks which will ultimately result in a machine that

More information

ISE In-Depth Tutorial 10.1

ISE In-Depth Tutorial 10.1 ISE In-Depth Tutorial 10.1 R Xilinx is disclosing this Document and Intellectual Property (hereinafter the Design ) to you for use in the development of designs to operate on, or interface with Xilinx

More information

5.4 Microcontrollers I: Introduction

5.4 Microcontrollers I: Introduction 5.4 Microcontrollers I: Introduction Dr. Tarek A. Tutunji Mechatronics Engineering Department Philadelphia University, Jordan Microcontrollers: Introduction Microprocessors were described in the last three

More information

Enhanced Wireless Security System With Digital code lock using RF &GSM Technology

Enhanced Wireless Security System With Digital code lock using RF &GSM Technology ISSN (e): 2250 3005 Vol, 04 Issue, 7 July 2014 International Journal of Computational Engineering Research (IJCER) Enhanced Wireless Security System With Digital code lock using RF &GSM Technology 1 E.Supraja,

More information

9/14/2011 14.9.2011 8:38

9/14/2011 14.9.2011 8:38 Algorithms and Implementation Platforms for Wireless Communications TLT-9706/ TKT-9636 (Seminar Course) BASICS OF FIELD PROGRAMMABLE GATE ARRAYS Waqar Hussain firstname.lastname@tut.fi Department of Computer

More information

2. Scope of the DE0 Board and Supporting Material

2. Scope of the DE0 Board and Supporting Material 1 Getting Started with Altera s DE0 Board This document describes the scope of Altera s DE0 Development and Education Board and the supporting materials provided by the Altera Corporation. It also explains

More information

Using Altera MAX Series as Microcontroller I/O Expanders

Using Altera MAX Series as Microcontroller I/O Expanders 2014.09.22 Using Altera MAX Series as Microcontroller I/O Expanders AN-265 Subscribe Many microcontroller and microprocessor chips limit the available I/O ports and pins to conserve pin counts and reduce

More information

Optimising the resource utilisation in high-speed network intrusion detection systems.

Optimising the resource utilisation in high-speed network intrusion detection systems. Optimising the resource utilisation in high-speed network intrusion detection systems. Gerald Tripp www.kent.ac.uk Network intrusion detection Network intrusion detection systems are provided to detect

More information

Open Flow Controller and Switch Datasheet

Open Flow Controller and Switch Datasheet Open Flow Controller and Switch Datasheet California State University Chico Alan Braithwaite Spring 2013 Block Diagram Figure 1. High Level Block Diagram The project will consist of a network development

More information

Lesson 9: Challenges in Embedded System Design: Optimizing the Design Metrics and Formalism of System Design

Lesson 9: Challenges in Embedded System Design: Optimizing the Design Metrics and Formalism of System Design Lesson 9: Challenges in Embedded System Design: Optimizing the Design Metrics and Formalism of System Design 1 Amount and type of hardware needed Optimizing the microprocessors, ASIPs and single purpose

More information

On the use of programmable logic in FabLabs

On the use of programmable logic in FabLabs 09.09.2013 Self introduction Electrical Engineer Self employed: Focus: Embedded Systems Motivation for being here: Providing and getting new ideas, make an offer, meeting interesting people Source: http://opensourceecology.org

More information

Best Practises for LabVIEW FPGA Design Flow. uk.ni.com ireland.ni.com

Best Practises for LabVIEW FPGA Design Flow. uk.ni.com ireland.ni.com Best Practises for LabVIEW FPGA Design Flow 1 Agenda Overall Application Design Flow Host, Real-Time and FPGA LabVIEW FPGA Architecture Development FPGA Design Flow Common FPGA Architectures Testing and

More information

Xilinx ISE. <Release Version: 10.1i> Tutorial. Department of Electrical and Computer Engineering State University of New York New Paltz

Xilinx ISE. <Release Version: 10.1i> Tutorial. Department of Electrical and Computer Engineering State University of New York New Paltz Xilinx ISE Tutorial Department of Electrical and Computer Engineering State University of New York New Paltz Fall 2010 Baback Izadi Starting the ISE Software Start ISE from the

More information

IS1200/IS1500. Lab4 Logic Design

IS1200/IS1500. Lab4 Logic Design IS1200/IS1500 Lab4 Logic Design Introduction The purpose of this lab is to give a hands-on experience of using gates and digital building blocks. These build blocks are then used in the next lab where

More information

Quartus II Introduction Using VHDL Design

Quartus II Introduction Using VHDL Design Quartus II Introduction Using VHDL Design This tutorial presents an introduction to the Quartus R II CAD system. It gives a general overview of a typical CAD flow for designing circuits that are implemented

More information

Nurve Networks. Chameleon AVR Credit Card Sized Computers GENERAL OVERVIEW

Nurve Networks. Chameleon AVR Credit Card Sized Computers GENERAL OVERVIEW Nurve Networks Chameleon AVR Credit Card Sized Computers GENERAL OVERVIEW The Chameleon AVR 8-Bit is the evolution of the high performance, small footprint, application development board. Similar to the

More information

NIOS II Based Embedded Web Server Development for Networking Applications

NIOS II Based Embedded Web Server Development for Networking Applications NIOS II Based Embedded Web Server Development for Networking Applications 1 Sheetal Bhoyar, 2 Dr. D. V. Padole 1 Research Scholar, G. H. Raisoni College of Engineering, Nagpur, India 2 Professor, G. H.

More information

Computer Performance. Topic 3. Contents. Prerequisite knowledge Before studying this topic you should be able to:

Computer Performance. Topic 3. Contents. Prerequisite knowledge Before studying this topic you should be able to: 55 Topic 3 Computer Performance Contents 3.1 Introduction...................................... 56 3.2 Measuring performance............................... 56 3.2.1 Clock Speed.................................

More information

Industrial Automation Training Academy. PLC, HMI & Drives Training Programs Duration: 6 Months (180 ~ 240 Hours)

Industrial Automation Training Academy. PLC, HMI & Drives Training Programs Duration: 6 Months (180 ~ 240 Hours) nfi Industrial Automation Training Academy Presents PLC, HMI & Drives Training Programs Duration: 6 Months (180 ~ 240 Hours) For: Electronics & Communication Engineering Electrical Engineering Instrumentation

More information

Copyright Peter R. Rony 2009. All rights reserved.

Copyright Peter R. Rony 2009. All rights reserved. Experiment No. 1. THE DIGI DESIGNER Experiment 1-1. Socket Connections on the Digi Designer Experiment No. 2. LOGIC LEVELS AND THE 7400 QUADRUPLE 2-INPUT POSITIVE NAND GATE Experiment 2-1. Truth Table

More information

150127-Microprocessor & Assembly Language

150127-Microprocessor & Assembly Language Chapter 3 Z80 Microprocessor Architecture The Z 80 is one of the most talented 8 bit microprocessors, and many microprocessor-based systems are designed around the Z80. The Z80 microprocessor needs an

More information

Design of a Video Game

Design of a Video Game Tallinn University of Technology Dept. of Computer Engineering Chair of Digital Systems Design Design of a Video Game Project in IAY0070 HW/SW Co-design Anti Sullin 020633 IASM-21 04.2006 Project supervisor:

More information

Integrating Digital Logic Design and Assembly Programming Using FPGAs in the Classroom

Integrating Digital Logic Design and Assembly Programming Using FPGAs in the Classroom Integrating Digital Logic Design and Assembly Programming Using FPGAs in the Classroom William M. Jones and D. Brian Larkins Department of Computer Science and Information Systems Coastal Carolina University

More information

Life Cycle of a Memory Request. Ring Example: 2 requests for lock 17

Life Cycle of a Memory Request. Ring Example: 2 requests for lock 17 Life Cycle of a Memory Request (1) Use AQR or AQW to place address in AQ (2) If A[31]==0, check for hit in DCache Ring (3) Read Hit: place cache word in RQ; Write Hit: replace cache word with WQ RDDest/RDreturn

More information

VREFout CFG B TMS TCK TDI TDO CS ENSPI

VREFout CFG B TMS TCK TDI TDO CS ENSPI Using SPI to Control isppac80 and isppac81 October 2002 Application Note AN6037 Introduction This application note describes how to use the Serial Peripheral Interface (SPI) to adjust the gain, select

More information

Echtzeittesten mit MathWorks leicht gemacht Simulink Real-Time Tobias Kuschmider Applikationsingenieur

Echtzeittesten mit MathWorks leicht gemacht Simulink Real-Time Tobias Kuschmider Applikationsingenieur Echtzeittesten mit MathWorks leicht gemacht Simulink Real-Time Tobias Kuschmider Applikationsingenieur 2015 The MathWorks, Inc. 1 Model-Based Design Continuous Verification and Validation Requirements

More information

Circuit and System Representation. IC Designers must juggle several different problems

Circuit and System Representation. IC Designers must juggle several different problems Circuit and System Representation IC Designers must juggle several different problems Multiple levels of abstraction IC designs requires refining an idea through many levels of detail, specification ->

More information

CONTENTS PREFACE 1 INTRODUCTION 1 2 NUMBER SYSTEMS AND CODES 25. vii

CONTENTS PREFACE 1 INTRODUCTION 1 2 NUMBER SYSTEMS AND CODES 25. vii 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is CONTENTS PREFACE xv 1 INTRODUCTION 1 1.1 About Digital Design 1 1.2 Analog versus Digital 3 1.3 Digital Devices

More information

Implementation of DDR SDRAM Controller using Verilog HDL

Implementation of DDR SDRAM Controller using Verilog HDL IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p- ISSN: 2278-8735.Volume 10, Issue 2, Ver. III (Mar - Apr.2015), PP 69-74 www.iosrjournals.org Implementation of

More information

Digital Logic Design

Digital Logic Design Digital Logic Design: An Embedded Systems Approach Using VHDL Chapter 1 Introduction and Methodology Portions of this work are from the book, Digital Logic Design: An Embedded Systems Approach Using VHDL,

More information

Chapter 11. Using MAX II User Flash Memory for Data Storage in Manufacturing Flow

Chapter 11. Using MAX II User Flash Memory for Data Storage in Manufacturing Flow Chapter 11. Using MAX II User Flash Memory for Data Storage in Manufacturing Flow MII51011-1.1 Introduction Small capacity, non-volatile memory is commonly used in storing manufacturing data (e.g., manufacturer

More information

Networking Remote-Controlled Moving Image Monitoring System

Networking Remote-Controlled Moving Image Monitoring System Networking Remote-Controlled Moving Image Monitoring System First Prize Networking Remote-Controlled Moving Image Monitoring System Institution: Participants: Instructor: National Chung Hsing University

More information

C8051F020 Utilization in an Embedded Digital Design Project Course. Daren R. Wilcox Southern Polytechnic State University Marietta, Georgia

C8051F020 Utilization in an Embedded Digital Design Project Course. Daren R. Wilcox Southern Polytechnic State University Marietta, Georgia C8051F020 Utilization in an Embedded Digital Design Project Course Daren R. Wilcox Southern Polytechnic State University Marietta, Georgia Abstract In this paper, the utilization of the C8051F020 in an

More information

PART B QUESTIONS AND ANSWERS UNIT I

PART B QUESTIONS AND ANSWERS UNIT I PART B QUESTIONS AND ANSWERS UNIT I 1. Explain the architecture of 8085 microprocessor? Logic pin out of 8085 microprocessor Address bus: unidirectional bus, used as high order bus Data bus: bi-directional

More information

Introduction to Programmable Logic Controllers (PLC's)

Introduction to Programmable Logic Controllers (PLC's) Introduction to Programmable Logic Controllers (PLC's) Programmable Logic Controllers (PLC's) are microprocessor devices much like the PIC microcontroller. Their function is to control the operation of

More information

Chapter 2 Digital Components. Section 2.1 Integrated Circuits

Chapter 2 Digital Components. Section 2.1 Integrated Circuits Chapter 2 Digital Components Section 2.1 Integrated Circuits An integrated circuit (IC) is a small silicon semiconductor crystal, called a chip, containing the electronic components for the digital gates

More information