Lecture 10. Latches and Flip-Flops

Transcription

1 Logic Design Lecture. Latches and Flip-Flops Prof. Hyung Chul Park & Seung Eun Lee

2 Sequential Logic Outputs of sequential logic depend on current inputs and prior input values Sequential logic might explicitly remember certain previous inputs, or it might distill (encode) the prior inputs into a smaller amount of information called state The state is a set of bits that contain all the information about the past necessary to explain the future behavior of the circuit 2

3 . Introduction To construct a switching circuit has a memory, must introduce feedback to circuit Unstable state Stable states 3

4 Bistable Circuit Bistable circuit is the fundamental building block of other state elements A pair of inverters are connected in a loop Two outputs:, No inputs 4

5 Bistable Circuit Analysis Let s consider the two possible cases = : then = and = (consistent) I I2 = : then = and = (consistent) I I2 5

6 Bistable Circuit Analysis Bistable circuit stores bit of state in the state variable (or ) But, there are no inputs to control the state A subtle point is that the circuit could have a third possible state with both outputs approximately halfway between and (halfway between and Vdd) It is called a metastable state Vdd/2 I Vdd/2 Vdd/2 I2 Vdd/2 6

7 Bistable Circuit Even though the cross-coupled inverters can store a bit of information, they are not practical because they don t have inputs to control the state. Other bistable elements such as latches and flipflops provide inputs to control the value of the state variable 7

8 .2 Set-Reset Latch One of the simplest sequential circuits is the SR (Set/Reset) latch It is composed of 2 cross-coupled NOR gates It has 2 inputs (S, R) and 2 outputs ( and ) When the set input (S) is (and R = ), is set to Set makes the output () to When the reset input (R) is (and S = ), is reset to Reset makes the output () to R N SR Latch Symbol R S N2 S 8

9 .2 Set-Reset Latch Consider the four possible cases: a) S =, R = b) S =, R = R N c) S =, R = d) S =, R = S N2 9

10 .2 Set-Reset Latch a) S =, R = : then = and = R N S N2 b) S =, R = : then = and = R N S N2

11 .2 Set-Reset Latch c) S =, R = : then = prev and = prev We got Memory! prev = prev = R N R N S N2 S N2 d) S =, R = : then = and = Invalid state: NOT R N S N2

12 .2 Set-Reset Latch Timing Diagram R N S N2 2

13 .2 Set-Reset Latch Truth table and K-map 3

14 .2 Set-Reset Latch Switch Debouncing with an SR Latch 4

15 .2 Set-Reset Latch An alternative form of the SR Latch with NAND 5

16 .3 Gated D Latch D latch solves the problem with SR latch D latch blocks the invalid state when S = and R = D latch separates when and what the state should be changed D latch has 2 inputs (CLK, D) and 2 outputs (, ) CLK controls when the output changes D (data input) controls what the output changes to Avoids invalid case ( NOT when both S and R are ) D Latch Symbol D CLK 6

17 .3 Gated D Latch D latch operation When CLK =, D passes through to (D latch is transparent) When CLK =, holds its previous value (D latch is opaque) CLK D D R S R S CLK D CLK D X D S R X prev prev prev prev 7

18 .3 Gated D Latch When evaluating latch, it would be confusing if you think previous value and current value things To get a good intuition, think with waveform When CLK =, D latch transfers input data (D) to output () When CLK =, D latch maintains its previous value 8

19 .3 Gated D Latch Gated D latch Symbol and Truth Table G D 9

20 .4 Edge Triggered D Flip-Flop In digital logic design, it would be very convenient if we can store input data at a certain moment (not during the whole time interval like D latch) D flip-flop provides that functionality changes only on the rising edge of CLK When CLK rises from to, D passes through to Otherwise, holds its previous value Thus, a flip-flop is called an edge-triggered device because it is activated on the clock edge D Flip-Flop Symbols D 2

21 .4 Edge Triggered D Flip-Flop Two back-to-back latches (L and L2) controlled by complementary clocks When CLK = L is transparent L2 is opaque D passes through to N When CLK = L2 is transparent L is opaque N passes through to D CLK D L N CLK CLK D L2 Thus, on the edge of the clock (when CLK rises from to ) D effectively passes through to 2

22 .4 Edge Triggered D Flip-Flop Note that input data should not be changed around the clock edge for D flip-flop to work correctly CLK D CLK D N CLK D L L2 22

23 .4 Edge Triggered D Flip-Flop Setup and Hold times for an D F/F 23

24 .4 Edge Triggered D Flip-Flop Determination of Minimum clock period 24

25 .5 S-R Flip-Flop 25

26 .5 S-R Flip-Flop Implementation with latches Timing 26

27 .6 J-K Flip-Flop 27

28 .6 J-K Flip-Flop Master-slave J-K Flip-Flop changes on Rising Edge 28

29 .7 T Flip-Flop 29

30 .7 T Flip-Flop Implementation of T Flip-Flops J K T T 3

31 .8 Flip-Flops w/ Additional Inputs D F/F with Clear and Preset 3

32 .8 Flip-Flops w/ Additional Inputs Timing for D F/F w/ Async. Clear and Preset 32

33 .8 Flip-Flops w/ Additional Inputs D F/F with clock Enable CE D CE D CE D in CE 33