Digital Circuits Laboratory LAB no. 9. Flip flops

Transcription

1 (FF) are sequential logic circuits with 2 distinct stable states. hey have control inputs that cause the outputs to switch from one stable state to the other. hey are circuits with memory, because one can deduce the last applied command by analyzing the outputs. Because they are the basis of all sequential circuits, their applications are various: counters, registers, AM memories, etc. here are 4 types of flip flops: D -. - flip-flop his FF has to command inputs named (et) and (eset) and 2 complementary outputs and. he input is used to write the information in the circuit (by convention the information means logic ) and the input that deletes the information from the circuit. Both inputs are active on logic. he circuit s truth table is the following: tn tn+ n n n n+ n+ = n n+ = n n+ = n+ = n+ = n+ =?? he circuit operates like this: if both inputs are inactive ( n = n =) the circuit keeps the state ( n+ = n ). if the input is active ( n =, n =) the information is written into the circuit ( n+ =) no matter which is the previous state. if the input is active ( n =, n =) the information is deleted from the circuit ( n+ =) no matter which is the previous state. 49

2 the case n = n = has no sense, because is not logic to write and to delete the information in the same moment. he good working condition for this circuit is n n =. Above, t n is the actual moment, and n, n, n are the input and the output values at the present moment, and t n+ is the next moment, n+ is the output in this moment. For the circuit synthesis n+ is considered output signal. he arnaugh diagrams for the outputs are the following: n n n n n n X X X X n n n n For the synthesis, the de Morgan theorem will be used in order to implement the circuit with NAND gates only: ( ) ( ) n n n n n n n n ( n n n n n) n ( n n) hus, the circuit looks like in the next figure: n n n n he circuit has the inputs active on logic. If the inverters are taken out, the circuit will have the inputs active on logic. he above circuit can be implemented with NO gates only. For this we will group the cells containing logic : 5

3 n n n n n n X X X X n n ( n) n ( ) Applying the de Morgan theorem the equations become: ( ) ( ) n n n n n n n n ( ) ( ) n n n n n n n n In this case the circuit will look like in the following figure: n n n n he above circuit is an asynchronous one. he synchronous circuit is also available. It has the inputs activated by a clock signal (following figure). As long as is logic, the AND gates have the outputs in logic no matter which are the inputs and. In these conditions its state cannot be changed. When is logic then = and = and the circuit works like in the asynchronous version flip flop his kind of flip flop eliminates the flip flop indefinite state. It has 2 5

4 inputs and and a clock input in the synchronous version. a) Asynchronous - flip flop he truth table of this circuit is the following: t n t n+ n n n n+ n+ = n n+ = n n+ = n+ = n+ = n+ = n+ = n n+ = n he input has the same role as the input for the - flip flop and the input as. he difference is for == when instead of the indefinite state the output switches to the complementary one. he V associated diagrams are: n n n n n n n n n n n he above equations can be rewritten: he flip flop looks like: n n n n n n n n n n n n n n n n n n n 52

5 he block framed in the dotted square is a - flip flop. We can deduce immediately the connection equation between the two flip flops: n n n n n n Another implementation choice that comes from the above equations is the following: n n n, n n n and has the next schematic: b) ynchronous - flip flop he synchronous - flip flops are obtained by replacing the 2 inputs NAND gates cu 3 input gates, the clock being connected to the third: heir disadvantage is that for = the circuit oscillates. c) Master-slave - flip flop In order to eliminate the oscillation a master slave structure has been proposed. his is based on two pipelined - flip flops. he first flip flop (the master) stores the data on the positive edge of the clock signal, while the second (slave) is detached. When the clock is logic, the data is 53

6 transferred from master to slave, while the master is detached from the inputs. In the following figure it is shown the logic schematic of this circuit. he truth table associated with the master slave flip flop is: n n n+ n n he symbol signify the fact that the output changes on the negative edge of the clock signal. 3. flip flop In many applications the flip flop is used with the inputs connected at logic. his connection represents another type of flip flop: flip flop or counting cell. Its truth table is: n+ n n 54

7 he flip flop realizes the clock frequency division with 2. As long as =, the output changes its state every two clock transitions (every negative edge). his property makes it suitable for using in counter s construction. t t t 4. D flip flop D his circuit has an input called D (data) and a clock input (). Besides these, it has two asynchronous inputs and that have the highest priority. he value at the input at t n goes at the output at t n+, as we can notice from its truth table. t n t n+ D n n+ From the truth table we observe that n+ =D n. hus, the D flip flop introduces a delay of the input state. he output at the moment t n+ is the 55

8 same as the input at the t n (delay cell or memory cell). his circuit is useful for realizing static AM memories, registers but also counters. Generally, any type of flip flop can be replaced with other type using conversion schemes. 3. Lab work Print the Lab sheet below and complete it according to the indications. 56

9 LAB HEE. Input the flip flop with NAND gates in MaxPlusII and simulate the circuit. Draw the waveforms from the simulation on the grid below. Write the delay time and the logic values on the waveforms. Compare the results with the truth table. Introduce the inverters on the inputs, save as a new circuit and simulate again. Draw the waveforms in this case. 2. Input in MaxPlusII a flip flop (FF from the library) and simulate it. Draw the waveforms on the grid below, measure the delay and compare the results with the truth table. clk 3. Input a D flip flop (DFF in the library) and simulate it. Draw the waveforms below, measure the delay and compare the results with the truth table. clk D 57