CMSC 2833 Lecture 25

Transcription

1 .6. Basic Concepts A sequential circuit has memory whereas a combinational circuit has no memory. The output of a combinational circuit is the direct result of inputs to the circuit. A combinational circuit is independent of past inputs. Sequential circuits record previous results in flip-flops. A flip-flop stores a single bit and usually employed to store the previous state of the circuit..6. Clocks Figure.8 A Clock Signal Indicating Discrete Instances of Time State changes occur in sequential circuits only when the clock ticks. Circuits can change state on the rising edge, falling edge, or when the clock pulse reaches its highest voltage.

2 .6. Flip-Flops.6.. The Binary Cell (L) RE(L) Cross-coupled NAND Gate Cell RE RE + RE = + = = + = = + = = + = 4 = + = 5 = + = 6 = + = 7 = + = Retains state RE Don t Do (H) RE(H) Cross-coupled NOR Gate Cell

3 .6.. SR Flip-Flop S(H) (L) CLK(H) R(H) SR Flip-Flop RE(L) Present State Net State S R (t) (t + ) Undefined SR Flip-Flop Characteristic Table Retains state RE Don t Do (t) (t + ) S R SR Flip-Flop Ecitation Table.6.. D Flip-Flop (t) (t + ) S R X X SR Flip-Flop Ecitation Table

4 D(H) (L) CLK(H) RE(L) D Flip-Flop Present State Net State D (t) (t + ) D Flip-Flop Characteristic Table RE (t) (t + ) D D Flip-Flop Ecitation Table 4

5 .6..4 JK Flip-Flop J(H) (L) CLK(H) K(H) RE(L) JK Flip-Flop Present State Net State J K (t) (t + ) JK Flip-Flop Characteristic Table Retains state RE Toggle (t) (t + ) J K X X X X JK Flip-Flop Ecitation Table 5

6 .6..5 Flip-Flop Design. Create Characteristic Table.. Plot K-Maps for the Basic Cell.. Draw the Logic Diagram. 4. Complete the Ecitation Table. Eample: Design a clocked SR Flip-Flop Step. Augmented characteristic table m i S R n n+ RE Comment No Change Reset 4 5 Set 6 7 Prohibited Characteristic Table /RE Decoder Truth-Table n n+ RE -RE Cell Ecitation Table Step. Plot maps SR n SR n = S Step. Draw Logic Diagram S RE = R CLK R RE Clocked SR Flip-Flop 6

7 Step 4. Complete Ecitation Table n n+ S R Comment No Change Reset Set Reset No Change Set Epanded SR Ecitation Table n n+ S R SR Ecitation Table S CK R SR Rising Edge-Triggered Flip-Flop 7

8 Eample: Design a clocked Reset-dominant SR Flip-Flop Step. Augment characteristic table m i S R n n+ RE Comment No Change Reset 4 5 Set 6 7 Reset Characteristic Table /RE Decoder Truth-Table Step. Plot maps SR n RE SR n = SR Step. Draw Logic Diagram S RE = R CLK R RE Reset Dominant SR Flip-Flop Step 4. Complete Ecitation Table n n+ S R Comment No Change Reset Reset Dominant Set Reset Reset Dominant No Change Set Epanded SR Ecitation Table 8

9 n n+ S R SR Ecitation Table Problems:. Design a -dominant clocked SR flip-flop. This flip-flop is to always leave the basic cell in a condition if S and R are asserted together. a. Define the characteristic table b. Design a NAND cell-centered flip-flop. c. Define the ecitation table d. Draw the schematic symbol. Design an RS flip-flop that will leave the basic cell unchanged in S and R are asserted together. a. Define the characteristic table b. Design a NAND cell-centered flip-flop. c. Define the ecitation table d. Draw the schematic symbol. Design a flip-flop specified by the characteristic table below. J K n n a. Design a NAND cell-centered flip-flop. b. Define the ecitation table c. Draw the schematic symbol 9

10 .6..6 Flip-Flop Conversion. Create a combined characteristic table. Column labels on the characteristic table are assigned as follows... Put the inputs of the to-flip-flop leftmost. For eample, convert a RS Flip-Flop to a D-Latch Flip-Flop. D L.. Net, put n. Continuing our eample of converting a RS Flip-Flop to a D-Latch Flip- Flop. D L n.. Net, compute n+. Continuing our eample of converting a RS Flip-Flop to a D-Latch Flip-Flop. D L n n+.4. Net, put the inputs to the source (convert a) Flip-Flop. Continuing our eample of converting a RS Flip-Flop to a D-Latch Flip-Flop. D L n n+ R S.5. Net, find epressions for the inputs of the source (convert a) Flip-Flop. D D S D R DL

11 .6. Net, draw a logic diagram. D L S CLK C R Eample: Convert a D-Latch flip-flop to a T flip-flop.. Put the inputs of the to-flip-flop leftmost.. Net, put n. T. Net, compute n+. T n T n n+ 4. Net, put the inputs to the source (convert a) Flip-Flop. T n n+ D

12 5. Net, find epressions for the inputs of the source (convert a) Flip-Flop. n T D T D T T n n n

13 Null, Linda and Lobur, Julia Computer Organization and Architecture 4 th Ed., Jones & Bartlett Learning, 6, ISBN , p A Mu-Not flip-flop (MN flip-flop) behaves as follows: If M =, the flip-flop complements the current state. If M =, the net state of the flip-flop is equal to the value of N. a) Derive the characteristic table for the flip-flop. Solution:. Copy an eisting characteristic table. Present State Net State S R (t) (t + ) Retains state RE Undefined Don t Do SR Flip-Flop Characteristic Table. Erase values in the Net State column. Omit values in the m i column. Remove the title and comments. Change S to M and R to N. Present State Net State M N (t) (t + ). If M =, the flip-flop complements the current state. Present State Net State M N (t) (t + )

14 4. If M =, the net state of the flip-flop is equal to the value of N. Present State Net State M N (t) (t + ) MN Characteristic Table b) Show how a JK flip-flop can be converted to an MN flip-flop by adding gate(s) and an inverter(s). Solution:. Copy the MN Characteristic Table and append two columns to the right of the table. Label the columns J and K. Present State Net State M N (t) (t + ) J K MN Characteristic Table 4

15 . For each row in the augmented characteristic table, determine what values of J and K are needed to make the value of (t) change to the corresponding value of (t + ). The JK Flip-Flop Ecitation Table is employed to find the required values of J and K. Present State Net State M N (t) (t + ) J K X X X X X X X X MN Characteristic Table. Plot values for J and K. (t) (t + ) J K X X X X JK Flip-Flop Ecitation Table J K MN 6 4 MN J = M + N K = M + N 5

16 4. Draw the logic diagram. M N J CK K 6