VHDL Course. Hands-on exercise session 2

Transcription

1 VHDL Course Hands-on exercise session 2 A) Objectives To develop and execute relatively simple VHDL models, in order to improve understanding of: - VHDL environment - sequential statements - delays - component instantiation - assertions B) Modeling entity specification SM C1 C2 DX3U Figure 1: D-type flip-flop It is required to develop a behavioral model of a D-type flip-flop. The schematic symbol is given by Figure 1. DX3U is a LS master-slave D-type flip-flop with 3 MUXes. Its inputs are: normal data (, and ) and control data (C1 and C2). The outputs are and. The inputs are clocked in the input section when is low. This cell is a Level Sensitive Scan Design (LS) function clocked by the two active-low nonoverlapping clocks, for the input section and for the output section. When the scan mode control (SM) is high, scan data () is clocked in. All functions for this cell are synchronous. The function table of DX3U is represented by table 1. i designates the internal value which follows the selected input data when is low. (the output section) is updated when goes low. 1

2 Table 1: Function table input i low C1 C2 SM i X 1 0 X X 1 C) Problem definition Part 1: A behavioral model of the flip-flop entity 1) Develop a behavioral model of the D-type flip-flop entity. The model must be completely synchronous, i.e., using delta delays, it will not involve any discrete delays (the only real delays will appear in the clock waveform generated by the test entity). Possible models: Structural model 2 latches + 3 MUXes: Too much detail of internal behavior! Dataflow - 2 blocks with guards, guarded signal assignments, an internal signal for linking the two blocks (similarly with two processes): Still too complex. Use knowledge of correct behavior of the environment: Single process sensitive only to and, internal variable to memorize state: loaded by D on rising, output to on falling (assumption on clocks non-overlap) 2) Develop a test bench model for the entity, or use ModelSim environment. The signals, must be initialized to 1. The architecture of the tester entity is defined below: architecture One of tester is GenCKS: process variable cycles : integer := 0; <= '1', '0'after 2 ns, '1'after 4 ns; <= '1', '0' after 6 ns; 2

3 cycles := cycles + 1; assert cycles <= 10 report "end of simulation" severity failure; wait for 12 ns; end process GenCKS; Waveforms: process <= '0','1' after 1 ns; <= '1','0' after 13 ns; <= '0','1' after 25 ns; <= '1','0' after 37 ns; C1 <= '0','1' after 13 ns; C2 <= '0','1' after 25 ns; SM <= '0','1' after 37 ns; wait; end process Waveforms; end One; 3

4 Part 2: A structural model of a two bit counter entity 1) Use the flip-flop entity to describe a two bit counter entity which uses the mapping between ports described by Figure 2. Attention: In this model an output of an instance drives 2 output ports of the higher entity. Must use an internal signal and 2 output port association statements. 2) Develop a test bench model for the counter entity. The generation of clock waveforms is similar to the generation of Part 1, the additional waveforms are as follows: I1 <= '1' after 1 ns; Sin <= '1' after 49 ns; ld <= '1' after 1 ns, '0' after 13 ns; count <= '1' after 13 ns, '0' after 49 ns; scan <='1' after 49 ns, '0' after 72 ns; 1 0 count ld scan Sin I1 SM C1 C2 SM C1 C2 DX3U1 DX3U0 Sout I0 CL1 CL2 Figure 2: Two-bit scannable counter 4

5 Part 3 (optional) : Delays and verification of some timing constraints Modify the flip-flop model to include real delays (Table 2). The load C is passed as a generic constant, assertions are used to verify set-up time hold time and the clock width. Re-simulate the counter using this more detailed FF model. Table 2: Typical characteristics Characteristic Propagation to rise to fall to rise to fall Data set-up / rising Data hold/ rising Nominal value (ns) C C C C 2.0 > 0.0 C denotes load which should be included in your model as a generic constant. C can be approximated by the number of fanouts emerging from the signal. 5