Memory unit. 2 k words. n bits per word

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1 9- k address lines Read n data input lines Memory unit 2 k words n bits per word n data output lines 24 Pearson Education, Inc M Morris Mano & Charles R Kime

2 9-2 Memory address Binary Decimal Memory contents Pearson Education, Inc M Morris Mano & Charles R Kime

3 T 9- TABLE 9- Control Inputs to a Memory Chip Chip R/W Memory operation None to ed word Read from ed word 24 Pearson Education, Inc M Morris Mano & Charles R Kime

4 9-3 2 ns Clock T T2 T3 T4 T valid Memory enable Data input Data valid 75 ns (a) cycle Clock 2 ns T T2 T3 T4 T valid Memory enable Data output 24 Pearson Education, Inc M Morris Mano & Charles R Kime 65 ns (b) Read cycle Data valid

5 9-4 Select B S C B R C 24 Pearson Education, Inc M Morris Mano & Charles R Kime

6 9-5 Word Select B S C B R C Word Word 2 n Select Word S R Word 2 n S R (b) Symbol 24 Pearson Education, Inc M Morris Mano & Charles R Kime (a) Logic diagram Read

7 9-6 4-to-6 Decoder Word A 3 A A 2 A A A A 6 RAM A Data input Data output Memory enable (a) Symbol put Data output 24 Pearson Education, Inc M Morris Mano & Charles R Kime Chip (b) Block diagram

8 9-7 Row decoder 2-to-4 Decoder A 3 A Row put Column 2 3 Data output Column decoder 2-to-4 Decoder with enable 2 2 Enable 24 Pearson Education, Inc M Morris Mano & Charles R Kime A A Chip

9 9- A 2 A Row decoder 2-to-4 Decoder Row put put Column decoder Column -to-2 Decoder with enable 2 Enable Data output Data output 24 Pearson Education, Inc M Morris Mano & Charles R Kime A Chip

10 9-9 64K RAM Input data 6 DATA ADRS Output data Chip R/W 24 Pearson Education, Inc M Morris Mano & Charles R Kime

11 9- Lines Lines Input data 6 Memory enable EN 3 2-to-4 decoder 2 64K RAM DATA ADRS R/W 65,535 64K RAM DATA ADRS R/W 65,536 3,7 64K RAM DATA ADRS R/W 3,72 96,67 64K RAM DATA 24 Pearson Education, Inc M Morris Mano & Charles R Kime ADRS R/W 96,6 262,43 Output data

12 9-6 input data lines 6 64K RAM 64K RAM 6 DATA ADRS 6 DATA ADRS Chip R/W R/W 6 output data lines 24 Pearson Education, Inc M Morris Mano & Charles R Kime

13 9-2 Select B T C To Pump D (a) (b) (c) Select B D C (d) (e) C D model (h) (f) (g) 24 Pearson Education, Inc M Morris Mano & Charles R Kime

14 9-3 Word Select B D C C D model Word D Word Word 2 n Select D D C D model Word 2 n D Sense amplifier (b) Symbol 24 Pearson Education, Inc M Morris Mano & Charles R Kime (a) Logic diagram Read

15 9-4 Refresh controller Refresh counter Row address Row address register Row decoder DRAM bit slice DRAM bit slice DRAM bit slice RAS Row timing CAS Column timing Logic Input/Output Logic R/W OE Column address Column address register Column decoder 24 Pearson Education, Inc M Morris Mano & Charles R Kime /

16 9-5 2 ns Clock T T2 T3 T4 T Row Column RAS CAS Output enable Data input 2 ns Data valid 75 ns (a) cycle Clock T T2 T3 T4 T Row Column RAS CAS Output enable Data output 24 Pearson Education, Inc M Morris Mano & Charles R Kime Hi-Z 65 ns (b) Read cycle Data valid

17 T 9-2 TABLE 9-2 DRAM Types Type Abbreviation Description Fast Page Mode DRAM Extended Data Output DRAM FPM DRAM EDO DRAM Takes advantage of the fact that, when a row is accessed, all of the row values are available to be read out By changing the column address, data from different addresses can be read out without reapplying the row address and waiting for the delay associated with reading out the row cells to pass if the row portion of the addresses match Extends the length of time that the DRAM holds the data values on its output, permitting the CPU to perform other tasks during the access since it knows the data will still be available Synchronous DRAM SDRAM Operates with a clock rather than being asynchronous This permits a tighter interaction between memory and CPU, since the CPU knows exactly when the data will be available SDRAM also takes advantage of the row value availability and divides memory into distinct banks, permitting overlapped accesses Double Data Rate Synchronous DRAM DDR SDRAM The same as SDRAM except that data output is provided on both the negative and the positive clock edges Rambus DRAM RDRAM A proprietary technology that provides very high memory access rates using a relatively narrow bus Error-Correcting Code 24 Pearson Education, Inc M Morris Mano & Charles R Kime ECC May be applied to most of the DRAM types above to correct single bit data errors and often detect double errors

18 9-6 CLK WE RAS CAS A(:) Control Refresh counter Row address mux Row address latches Row decoder Memory cell array D(7:) put register I/O register Column decoder Col address counter put register 24 Pearson Education, Inc M Morris Mano & Charles R Kime

19 9-7 CLK t CLK WE RAS CAS ADDRESS ROW COL DATA B B2 B3 B t RC 24 Pearson Education, Inc M Morris Mano & Charles R Kime

20 9- CLK t CLK WE t PACK ROW ROW COL DATA DATA t RC 24 Pearson Education, Inc M Morris Mano & Charles R Kime

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