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2 FIGURE 2 3-Bit Adder. FIGURE 3 Half Adder. Design A partially completed truth table for a full adder is given in Figure 4. The table indicates the values of the outputs for every possible input, and thus completely specifies the operation of a full adder. As is common, the inputs are shown in binary numeric order. The values for SUM are given, but the CARRY_OUT column is left blank. Complete the table by filling in the correct values for CARRY_OUT so that adders connected as in Figure 2 will perform valid addition. The SUM output can be produced from the inputs by connecting two XOR gates as shown in Figure 5. You should convince yourself that this circuit produces the outputs for SUM as given in the table. Using only two-input logic gates (AND, OR, XOR) and inverters (NOT), design a circuit that takes A, B, and CARRY_IN as its inputs and produces the CARRY_OUT output, as shown in Figure 6. Try to use the fewest number of gates possible. For now, you may have to use trial and error to find a set of gates that works. We will soon be learning a systematic way to do this using Boolean algebra. Inputs Outputs CARRY_IN B A CARRY_OUT SUM FIGURE 4 Partially completed truth table for a full adder. Schematic Now that you know how to produce both the SUM and CARRY_OUT outputs using simple logic gates, you might want to construct a working full adder circuit using real hardware. One way to do this is to enter the schematic representation of your logic into a software package that is capable of programming the schematic into an 2

3 FIGURE 5 Schematic for SUM logic.? FIGURE 6 Schematic of CARRY_OUT logic (for you to complete). integrated circuit. We will be using the Xilinx ISE 4 software for these purposes. The Xilinx software is a powerful and popular commercial suite of applications used by hardware designers. You will need a Windows computer with this software installed. First, you will learn how to start a new project in Xilinx. Enter the Xilinx software by clicking on the icon for Project Navigator, found on the desktop of the Engineering Server. Or you can select Start Program Xilinx ISE 4 Project Navigator. This will open the Project Navigator, shown in Figure 7, which will always serve as your entry point into the Xilinx applications. FIGURE 7 Xilinx project navigator. In the Project Navigator window, choose File New Project from the pull-down menu. In the New Project dialog window shown in Figure 8, type the desired location in the Project Location field, or browse to the directory under which you want to create your new project directory using the browse button next to the Project Location field. The next step is to enter lab1_xx (where xx are your initials) as the name of your project. Use the pulldown arrow to select the value for each property of Project Device Options. Select the device family to be Virtex 3

5 FIGURE 10 Xilinx Schematic Editor. FIGURE 11 Circuit symbols window. You ll notice that the library of symbols is quite large. The available symbols range from the simple logic gates that we will be using for now to more complex circuit components. Scroll down and select the xor2 symbol. (Al- 5

7 FIGURE 12 Project navigator window after schematic input. default timing constraints for the testbench waveform. Now, HDL Bencher will be launched, as shown in Figure 13. FIGURE 13 HDL Bencher window. Note that, before initializing the inputs, you should ensure that you have chosen View Decimal or selected the 10 Display in Decimal button in the HDL Bencher toolbar. You can then enter the input stimulus in the blue area in each cell. For example, click cell A so that it is set high at even cycles 2, 4, 6 and 8. You can drag the blue vertical line to set cycle 8 to be the end of the test. Similarly for input B and CARRY_IN: B is set high at cycles 3, 4, 7 and 8, while CARRY_IN is set high at cycles 5, 6, 7 and 8. Now you can save the testbench waveform by selecting File Save waveform or by clicking the Save icon before exiting HDL Bencher. In the Project Navigator window, you will see that the lab1.tbw file is listed as one of the source files associated with the schematic file. Select the lab1.tbw file, and you will see the ModelSim Simulator in the Processes for Current Source window. You can expand the option by click the left side +. In the list, as shown in Figure 14, double click Simulate Behavioral Verilog Model. When ModelSim is launched, you are able to see the waveform in the time domain. If there is an error in launching ModelSim, look for error messages and correct them. Click the Zoom Full icon in the taskbar to see the whole waveform of the simulation results. Both input and output bus values can be set to be displayed in either 7

8 FIGURE 14 Choose Simulate Behavioral Verilog Model from ModelSim Simulator. Hex, Decimal or Binary. Choose Radix Binary/Decimal/Hexadecimal. When the output values are correct, you have a working full adder! Choose File Print to print a copy of your waveforms to turn in. If the result is not what you expected, go back to the schematic and testbench waveform files and check the design. Congratulations on your completion of lab 1! 8

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