SN54/74LS192 SN54/74LS193

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1 PRESEABLE BCD/DECADE UP/DOWN COUNER PRESEABLE 4-BI BINARY UP/DOWN COUNER he SN4/74LS2 is an UP/DOWN BCD Decade (842) Counter and the SN4/74LS3 is an UP/DOWN MODULO-6 Binary Counter. Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously. he outputs change state synchronous with the LOW-to-HIGH traitio on the clock inputs. Separate erminal Count Up and erminal Count Down outputs are provided which are used as the clocks for a subsequent stages without extra logic, thus simplifying multistage counter desig. Individual preset inputs allow the circuits to be used as programmable counters. Both the Parallel Load () and the Master Reset () inputs asynchronously override the clocks. Low Power... mw ypical Dissipation High Speed MHz ypical Count Frequency Synchronous Counting Asynchronous Master Reset and Parallel Load Individual Preset Inputs Cascading Circuitry Internally Provided Input Clamp Diodes Limit High Speed ermination Effects SN4/74LS2 SN4/74LS3 PRESEABLE BCD/ DECADE UP/DOWN COUNER PRESEABLE 4-BI BINARY UP/DOWN COUNER 6 6 LOW POWER SCHOKY J SUFFIX CERAMIC CASE N SUFFIX ASIC CASE VCC CONNECION DIAGRAM DIP (OP VIEW) P0 CD CU P2 P3 6 D SUFFIX SOIC CASE 7B NOE: he Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. ORDERING INFORMAION SN4LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXD SOIC P 0 CPD 2 3 GND LOGIC SYMBOL PIN NAMES LOADING (Note a) 0 CPD n CD CU Count Up Clock Pulse Input Count Down Clock Pulse Input Asynchronous Master Reset (Clear) Input Asynchronous Parallel Load (Active LOW) Input Parallel Data Inputs Flip-Flop Outputs (Note b) erminal Count Down (Borrow) Output (Note b) erminal Count Up (Carry) Output (Note b) HIGH 0. U.L. 0. U.L. 0. U.L. 0. U.L. 0. U.L. 0 U.L. 0 U.L. 0 U.L. NOES: a. L Unit Load (U.L.) = 40 µa HIGH/.6 ma LOW. b. he Output LOW drive factor is 2. U.L. for Military (4) and U.L. for Commercial (74) b. emperature Ranges. LOW 0.2 U.L. 0.2 U.L. 0.2 U.L. 0.2 U.L. 0.2 U.L. (2.) U.L. (2.) U.L. (2.) U.L. 4 CPD 4 P0 P P2 CD VCC = PIN 6 GND = PIN 8 P3 CU 2 3 FAS AND LS L DAA -

2 SN4/74LS2 SN4/74LS3 SAE DIAGRAMS LS2 LOGIC EUAIONS FOR ERMINAL COUN CU = 0 3 CD = CPD LS3 LOGIC EUAIONS FOR ERMINAL COUN CU = CD = CPD LS2 COUN UP COUN DOWN LS3 LOGIIAGRAMS (LOAD) (UP COUN) P0 P P2 P3 0 2 CU (CARRY OUPU) S D S D S D S D CPD 4 (DOWN COUN) 4 (CLEAR) CD (BORROW OUPU) VCC = PIN 6 GND = PIN 8 = PIN NUMBERS LS2 FAS AND LS L DAA -2

3 SN4/74LS2 SN4/74LS3 LOGIIAGRAMS (continued) (LOAD) (UP COUN) P0 P P2 P3 0 2 CU (CARRY OUPU) S D S D S D S D CPD 4 (DOWN COUN) 4 (CLEAR) CD (BORROW OUPU) LS3 VCC = PIN 6 GND = PIN 8 = PIN NUMBERS FAS AND LS L DAA -3

4 SN4/74LS2 SN4/74LS3 FUNCIONAL DESCRIPION he LS2 and LS3 are Asynchronously Presettable Decade and 4-Bit Binary Synchronous UP/ DOWN (Reversable) Counters. he operating modes of the LS2 decade counter and the LS3 binary counter are identical, with the only difference being the count sequences as noted in the State Diagrams. Each circuit contai four master/slave flip-flops, with internal gating and steering logic to provide master reset, individual preset, count up and count down operatio. Each flip-flop contai JK feedback from slave to master such that a LOW-to-HIGH traition on its input causes the slave, and thus the output to change state. Synchronous switching, as opposed to ripple counting, is achieved by driving the steering gates of all stages from a common Count Up line and a common Count Down line, thereby causing all state changes to be initiated simultaneously. A LOW-to-HIGH traition on the Count Up input will advance the count by one; a similar traition on the Count Down input will decrease the count by one. While counting with one clock input, the other should be held HIGH. Otherwise, the circuit will either count by twos or not at all, depending on the state of the first flip-flop, which cannot toggle as long as either Clock input is LOW. he erminal Count Up (CU) and erminal Count Down (CD) outputs are normally HIGH. When a circuit has reached the maximum count state ( for the LS2, for the LS3), the next HIGH-to-LOW traition of the Count Up Clock will cause CU to go LOW. CU will stay LOW until goes HIGH again, thus effectively repeating the Count Up Clock, but delayed by two gate delays. Similarly, the CD output will go LOW when the circuit is in the zero state and the Count Down Clock goes LOW. Since the C outputs repeat the clock waveforms, they can be used as the clock input signals to the next higher order circuit in a multistage counter. Each circuit has an asynchronous parallel load capability permitting the counter to be preset. When the Parallel Load () and the Master Reset () inputs are LOW, information present on the Parallel Data inputs (P0, P3) is loaded into the counter and appears on the outputs regardless of the conditio of the clock inputs. A HIGH signal on the Master Reset input will disable the preset gates, override both Clock inputs, and latch each output in the LOW state. If one of the Clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH traition of that Clock will be interpreted as a legitimate signal and will be counted. MODE SELEC ABLE CPD MODE H X X X Reset (Asyn.) L L X X Preset (Asyn.) L H H H No Change L H H Count Up L H H Count Down L = LOW Voltage Level H = HIGH Voltage Level X = Don t Care = LOW-to-HIGH Clock raition FAS AND LS L DAA -4

5 SN4/74LS2 SN4/74LS3 GUARANEED OPERAING RANGES Symbol Parameter Min yp Max Unit VCC Supply Voltage V A Operating Ambient emperature Range C IOH Output Current High 4, ma IOL Output Current Low ma DC CHARACERISICS OVER OPERAING EMPERAURE RANGE (unless otherwise specified) Limits Symbol Parameter Min yp Max Unit est Conditio i VIH Input HIGH Voltage 2.0 V VIL Input LOW Voltage V Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VIK Input Clamp Diode Voltage 0.6. V VCC = MIN, IIN = 8 ma VOH VOL Output HIGH Voltage Output LOW Voltage V VCC = MIN, IOH = MAX, VIN = VIH V or VIL per ruth able 4, V IOL = 4.0 ma VCC = VCC MIN, VIN =VIL or VIH V IOL = 8.0 ma per ruth able IIH Input HIGH Current 20 µa VCC = MAX, VIN = 2.7 V 0. ma VCC = MAX, VIN = 7.0 V IIL Input LOW Current 0.4 ma VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note ) ma VCC = MAX ICC Power Supply Current 34 ma VCC = MAX Note : Not more than one output should be shorted at a time, nor for more than second. AC CHARACERISICS (A = 2 C) Limits Symbol Parameter Min yp Max Unit est Conditio i fmax Maximum Clock Frequency 2 32 MHz Input to CU Output CPD Input to CD Output Clock to VCC =.0 V CL = pf to Input to Any Output 23 3 FAS AND LS L DAA -

6 SN4/74LS2 SN4/74LS3 AC SEUP REUIREMENS (A = 2 C) Symbol Parameter Min Limits yp Max Unit est Conditio i tw Any Pulse Width 20 ts Data Setup ime 20 th Data Hold ime.0 VCC =0V.0 trec Recovery ime 40 DEFINIIONS OF ERMS SEUP IME (ts) is defined as the minimum time required for the correct logic level to be present at the logic input prior to the traition from LOW-to-HIGH in order to be recognized and traferred to the outputs. HOLD IME (th) is defined as the minimum time following the traition from LOW-to-HIGH that the logic level must be maintained at the input in order to eure continued recognition. A negative HOLD IME indicates that the correct logic level may be released prior to the traition from LOW-to-HIGH and still be recognized. RECOVERY IME (trec) is defined as the minimum time required between the end of the reset pulse and the clock traition from LOW-to-HIGH in order to recognize and trafer HIGH data to the outputs. FAS AND LS L DAA -6

7 SN4/74LS2 SN4/74LS3 AC WAVEFORMS or CPD tw Figure or CPD CU or CD n NOE: = LOW Figure 2 Figure 3 tw or CPD tw trec n Figure 4 Figure ts(h) th(h) ts(l) th(l) tw trec n = P = P or CPD * he shaded areas indicate when the input is permitted * to change for predictable output performance Figure 6 Figure 7 FAS AND LS L DAA -7

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