Combinational circuit Memory elements. Fig. 5-1 Block Diagram of Sequential Circuit Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.
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1 Inputs ombinational circuit Memory elements Outputs Fig. 5- Block Diagram of Sequential ircuit 22 Prentice Hall, Inc.
2 Inputs ombinational circuit Outputs Flip-flops lock pulses (a) Block diagram (b) Timing diagram of clock pulses Fig. 5-2 Synchronous locked Sequential ircuit 22 Prentice Hall, Inc.
3 R (reset) S (set) Q Q S R Q Q (after S, R ) (after S, R ) (a) Logic diagram (b) Function table Fig. 5-3 SR Latch with NOR Gates 22 Prentice Hall, Inc.
4 S (set) R (reset) Q Q S R Q Q (after S, R ) (after S, R ) (a) Logic diagram (b) Function table Fig. 5-4 SR Latch with NAND Gates 22 Prentice Hall, Inc.
5 S Q S R Next state of Q R Q X X No change No change Q ; Reset state Q ; set state Indeterminate (a) Logic diagram (b) Function table Fig. 5-5 SR Latch with ontrol Input 22 Prentice Hall, Inc.
6 D Q Q D X Next state of Q No change Q ; Reset state Q ; Set state (a) Logic diagram (b) Function table Fig. 5-6 D Latch 22 Prentice Hall, Inc.
7 S S D R R SR SR Fig. 5-7 Graphic Symbols for Latches D 22 Prentice Hall, Inc.
8 (a) Response to positive level (b) Positive-edge response (c) Negative-edge response Fig. 5-8 lock Response in Latch and Flip-Flop 22 Prentice Hall, Inc.
9 D D D latch (master) Y D D latch (slave) Q LK Fig. 5-9 Master-Slave D Flip-Flop 22 Prentice Hall, Inc.
10 LK S R Q Q D Fig. 5- D-Type Positive-Edge-Triggered Flip-Flop 22 Prentice Hall, Inc.
11 D D (a) Positive-edge (a) Negative-edge Fig. 5- Graphic Symbol for Edge-Triggered D Flip-Flop 22 Prentice Hall, Inc.
12 J D Q J K LK Q K (a) ircuit diagram (b) Graphic symbol Fig. 5-2 JK Flip-Flop 22 Prentice Hall, Inc.
13 T J T D T K (a) From JK flip-flop (b) From D flip-flop (c) Graphic symbol Fig. 5-3 T Flip-Flop 22 Prentice Hall, Inc.
14 LK S R Q Q D Reset (a) ircuit diagram 22 Prentice Hall, Inc. Data LK Reset D R (b) Graphic symbol Q Q R X D X Q Q (b) Function table Fig. 5-4 D Flip-Flop with Asynchronous Reset
15 x D A A D B B LK y 22 Prentice Hall, Inc. Fig. 5-5 Example of Sequential ircuit
16 / / / / / / / / Fig. 5-6 State Diagram of the ircuit of Fig Prentice Hall, Inc.
17 Present state Inputs Next state x y LK D A A x y A (a) ircuit diagram (b) State table,,,, (c) State diagram 22 Prentice Hall, Inc. Fig. 5-7 Sequential ircuit with D Flip-Flop
18 J A x K J B K LK Fig. 5-8 Sequential ircuit with JK Flip-Flop 22 Prentice Hall, Inc.
19 Fig. 5-9 State Diagram of the ircuit of Fig Prentice Hall, Inc.
20 x T A y R T B / / R / / LK Reset (a) ircuit diagram (b) State diagram 22 Prentice Hall, Inc. Fig. 5-2 Sequential ircuit with T Flip-Flops
21 ns ns 2ns 3ns 4ns 5ns 6ns 7ns 8ns 9ns testtcircuit.x testtcircuit.lk testtcircuit.rst testtcircuit.y testcircuit.a testcircuit.b Fig. 5-2 Simulation Output of HDL Example Prentice Hall, Inc.
22 / a / / / / b / c / g d / / e / / / f / / Fig State Diagram 22 Prentice Hall, Inc.
23 / / a / / e b / c / / / d / / Fig Reduced State Diagram 22 Prentice Hall, Inc.
24 S / S / S 3 / S 2 / Fig State Diagram for Sequence Detector 22 Prentice Hall, Inc.
25 A Bx B A x D A Ax Bx D B Ax B x y AB Fig Maps for Sequence Detector 22 Prentice Hall, Inc.
26 D A x D B B LK y 22 Prentice Hall, Inc. Fig Logic Diagram of Sequence Detector
27 A Bx B A Bx X X B X X A X X X X A x x J A Bx K A Bx A Bx B X X A Bx B X X A X X A X X x x J B x K B (A x) 22 Prentice Hall, Inc. Fig Maps for J and K Input Equations
28 x J A K A J B K B LK Fig Logic Diagram for Sequential ircuit with JK Flip-Flops 22 Prentice Hall, Inc.
29 Fig State Diagram of 3-Bit Binary ounter 22 Prentice Hall, Inc.
30 A A 2 A T A2 A A T A A T A Fig. 5-3 Maps for 3-Bit Binary ounter 22 Prentice Hall, Inc.
31 A 2 A A T T T LK Fig. 5-3 Logic Diagram of 3-Bit Binary ounter 22 Prentice Hall, Inc.
32 x y Full adder S Q D K Fig. P Prentice Hall, Inc.
33 A A B B T T LK Fig. P Prentice Hall, Inc.
34 / / / / / / / / / / Fig. P Prentice Hall, Inc.
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