FlipFlops. Outline: 2. Timing noise


 Rosamund Hawkins
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1 Outline: 2. Timing noise FlipFlops Signal races, glitches FPGA example ( assign bad) Synchronous circuits and memory Logic gate example 4. FlipFlop memory RSlatch example D and JK flipflops Flipflops in FPGAs Synchronous circuit design with FPGAs FPGA example ( always good). Parallel circuit design with FPGAs.
2 Timing noise Amplitude Noise A digital circuit is very immune to amplitude noise, since it can only have two values (Low or High, True or False, 0 or 1). Digital electronics circuits typically have error rates smaller than 1 part in 10 9 (no error correction). Timing Noise Just like an analog circuit, a digital circuit can experience timing noise. Fortunately, good clocks are cheap and easily available, and a good design will eliminate the effects of timing noise. Timing issues/errors can easily produce amplitude noise (bit errors).
3 Signal Race The timing delays produced by wires and logic gates can produce unwanted (illogical) outputs. Example: 3input NAND gate A B AB C Y A B C Time ideal Y
4 Signal Race The timing delays produced by wires and logic gates can produce unwanted (illogical) outputs. Example: 3input NAND gate A B AB C Y A B C AB resulting Y 2x gate delay Time If gate delays are too long output pulse could disappear
5 Signal Race The timing delays produced by wires and logic gates can produce unwanted (illogical) outputs. Example: 3input NAND gate A B AB C Y A B C AB 2x gate delay Time actual Y Pulse is shorter than expected and delayed
6 A Signal Race with Glitch AB XOR B A Y A L L B L H Y L H B AB [diagram courtesy of Altera Inc.] H H L H H L resulting resulting A B A B AB AB Inverter delay Inverter delay + component differences Time resulting Y [Figure adapted from Principles of Electronics: Analog & Digital by L. R. Fortney]
7 A Signal Race with Glitch AB XOR B A Y A L L B L H Y L H B AB [diagram courtesy of Altera Inc.] H H L H H L A B A B Time real real real AB AB Y [Figure adapted from Principles of Electronics: Analog & Digital by L. R. Fortney]
8 Glitches with FPGAs Quartus II will simulate glitches glitches
9 Asynchronous Design Asynchronous design requires very careful attention to signal delays to avoid producing glitches and other spurious signals. Glitches will produce false data and can produce very wrong results e.g. a glitch on the mostsignificantbit will produce a factor of 2 error. Asynchronous design can produce very fast digital circuits, but is generally avoided due to more difficult design.
10 Synchronous Design The use of memory and a clock can eliminate signal races and glitches. A B AB flip flop clock C in flip flop out Y Basic flipflop operation clock The flipflop will record and output the value at the input if the clock is HIGH. If the clock goes LOW, then the flipflop does not change its value or output. Glitches are eliminated if 1. The clock HIGH and LOW times are longer than any gate delays. 2. The inputs are synchronized to the clock.
11 A B C Synchronous Timing AB flip flop flip flop clock Y clock clock A B C Flipflop AB Flipflop C resulting Y 2x gate delay Time Guaranteed minimum signal pulse
12 Dtype EdgeTriggered FlipFlop Generally, the flipflop changes state on a clock signal edge, not the level. The flipflop takes the value just before the clock edge. clock D t s t h S or PRE Q input D Q output For 74LS74: minimum t s = 20 ns minimum t h = 5 ns clock Q R or CLR [Texas Instruments 74LS74 flipflop datasheet] Note: A flipflop saves information (i.e. 1 bit); it does not modify it.
13 Dtype EdgeTriggered FlipFlop Generally, the flipflop changes state on a clock signal edge, not the level. The flipflop takes the value just before the clock edge. clock D t s t h risingedge trigger S or PRE Q input D Q output For 74LS74: minimum t s = 20 ns minimum t h = 5 ns clock Q R or CLR [Texas Instruments 74LS74 flipflop datasheet] Note: A flipflop saves information (i.e. 1 bit); it does not modify it.
14 A B C clock A B Synchronous Timing (revisited) AB flip flop flip flop clock clock Y C Flipflop AB Time Flipflop C resulting Y
15 How does a flipflop work? Basic flipflop: the SR latch Logic table Q 0 = value before S&R changes R = 0 & S = 0: S = 0 & assume Q = 0 Q = 1. S = 0 & assume Q = 1 Q = 1. R = 0 & assume Q = 0 Q = 1. R = 0 & assume Q = 1 Q = 1.
16 How does a flipflop work? Basic flipflop: the SR latch Logic table Q 0 = value before S&R changes R = 0 & S = 0: S = 0 & assume Q = 0 Q = 1. S = 0 & assume Q = 1 Q = 1. R = 0 & assume Q = 0 Q = 1. consistent R=0 & S=0 Q=1 & Q=1 R = 0 & assume Q = 1 Q = 1.
17 How does a flipflop work? Basic flipflop: the SR latch Logic table Q 0 = value before S&R changes R = 0 & S = 1: S = 1 & assume Q = 0 Q = 1. S = 1 & assume Q = 1 Q = 0. R = 0 & assume Q = 0 Q = 1. R = 0 & assume Q = 1 Q = 1.
18 How does a flipflop work? Basic flipflop: the SR latch Logic table Q 0 = value before S&R changes R = 0 & S = 1: S = 1 & assume Q = 0 Q = 1. S = 1 & assume Q = 1 Q = 0. R = 0 & assume Q = 0 Q = 1. consistent R=0 & S=1 Q=0 & Q=1 R = 0 & assume Q = 1 Q = 1.
19 How does a flipflop work? Basic flipflop: the SR latch Logic table Q 0 = value before S&R changes R = 1 & S = 0: The opposite of R = 0 & S = 1 by symmetry.
20 How does a flipflop work? Basic flipflop: the SR latch Logic table Q 0 = value before S&R changes R = 1 & S = 1: S = 1 & assume Q = 0 Q = 1. S = 1 & assume Q = 1 Q = 0. R = 1 & assume Q = 0 Q = 1. R = 1 & assume Q = 1 Q = 0.
21 How does a flipflop work? Basic flipflop: the SR latch Logic table Q 0 = value before S&R changes R = 1 & S = 1: S = 1 & assume Q = 0 Q = 1. S = 1 & assume Q = 1 Q = 0. R = 1 & assume Q = 0 Q = 1. consistent R=1 & S=1 Q=1 & Q=0 consistent R=1 & S=1 Q=0 & Q=1 R = 1 & assume Q = 1 Q = 0.
22 How does a flipflop work? Basic flipflop: the SR latch Logic table Q 0 = value before S&R changes R = 1 & S = 1: S = 1 & assume Q = 0 Q = 1. S = 1 & assume Q = 1 Q = 0. R = 1 & assume Q = 0 Q = 1. R = 1 & assume Q = 1 Q = 0. consistent R=1 & S=1 Q=1 & Q=0 consistent R=1 & S=1 Q=0 & Q=1 Two settings are possible i.e. flipflop keeps its state.
23 SR Latch Switch Debouncer SR latch flipflops are not used much for memory, but they are used for debouncing switches. Switch Bounce: When a switch is toggled it will not go smoothly from HIGH to LOW, or vice versa. Volts bouncing switch Volts debounced switch time time R +5V R
24 Clocked Dtype Latch S Logic table R Clock Circuit Analysis: C = 1 & D = 1 S = 0 & R = 1. C = 1 & D = 0 S = 1 & R = 0. C = 0 & D = 1 S = 1 & R = 1. C = 0 & D = 0 S = 1 & R = 1.
25 Clocked Dtype Latch S Logic table R Clock Circuit Analysis: C = 1 & D = 1 S = 0 & R = 1. C = 1 & D = 0 S = 1 & R = 0. C = 0 & D = 1 S = 1 & R = 1. C = 0 & D = 0 S = 1 & R = 1. Clock HIGH: D sets the flipflop state Clock LOW: flipflop state is locked
26 Clocked Dtype Latch input D Q output Logic table clock Q Clock Circuit Analysis: C = 1 & D = 1 S = 0 & R = 1. C = 1 & D = 0 S = 1 & R = 0. C = 0 & D = 1 S = 1 & R = 1. C = 0 & D = 0 S = 1 & R = 1. Clock HIGH: D sets the flipflop state Clock LOW: flipflop state is locked
27 MasterSlave Dtype FlipFlop Note: The flipflop triggers on a the falling edge of the clock.
28 74LS74 Dtype edgetriggered flipflop [Texas Instruments 74LS74 flipflop datasheet] Both PRE and CLR behave like S and R inputs, respectively, on the SR latch. IMPORTANT: Both PRE and CLR must be high for normal Dtype operation. Note: The flipflop triggers on the rising edge of the clock.
29 74LS74 Dtype edgetriggered flipflop input D PRE Q output [Texas Instruments 74LS74 flipflop datasheet] clock CLR Q Both PRE and CLR behave like S and R inputs, respectively, on the SR latch. IMPORTANT: Both PRE and CLR must be high for normal Dtype operation. Note: The flipflop triggers on the rising edge of the clock.
30 JKtype flipflop Logic table for clock falling edge input J Q output J K Q n+1 clock input K C Q Q n 0 1 Q n JKtype flipflops are used in counters.
31 Flipflops in FPGAs Architecture of a single Logic Element inputs clock signals LUT CLOCK triggers Memory (a few bits) global local outputs feedback Frequently a Dtype FlipFlop FPGAs are already setup for synchronous circuit designs
32 Flipflops in FPGAs Architecture of a single Logic Element inputs clock signals LUT CLOCK triggers Memory (a few bits) global local outputs feedback Frequently a Dtype FlipFlop FPGAs are already setup for synchronous circuit designs
33 Synchronous programming in Verilog (I)
34 Synchronous programming in Verilog (I) Clock variable output register (i.e. flipflop memory )
35 Synchronous programming in Verilog (I) Clock variable output register (i.e. flipflop memory ) Read as always at the positive clock edge do the following always is the core command for synchronous programming, it should be used as frequently as possible. assign should be used as little as possible. It is only useful for DC type signals (signals that don t change).
36 Synchronous programming in Verilog (II) Quartus II circuit simulation
37 Synchronous programming in Verilog (II) Quartus II circuit simulation Clock Line No more glitches
38 How did the FPGA implement the circuit? Tools > Netlists > Technology Map Viewer
39 How did the FPGA implement the circuit? Tools > Netlists > Technology Map Viewer Dtype edgetriggered flipflops
40 Always use always _ A. Stummer, U. of Toronto.
41 Parallel programming in Verilog The always structure is used for exploiting the parallel processing features of the FPGA. Parallel processing must almost always be synchronous if several processes exchange data. Parallel and Sequential processing examples: Sequential (negedge clock) begin a = b; c = a; end Parallel (negedge clock) begin a <= b; c <= a; end
42 Parallel programming in Verilog The always structure is used for exploiting the parallel processing features of the FPGA. Parallel processing must almost always be synchronous if several processes exchange data. Parallel and Sequential processing examples: Sequential (negedge clock) begin a = b; c = a; end Parallel (negedge clock) begin a <= b; c <= a; end executed simultaneously c = b a = b c = a (previous value)
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