Sequential Circuits: Latches & Flip-Flops

Transcription

1 Sequential Circuits: Latches & Flip-Flops

2 Sequential Circuits Combinational Logic: Output depends only on current input Able to perform useful operations (add/subtract/multiply/encode/decode/ select[mux]/etc ) Require cascading of many structures Costly and inflexible 2

3 Sequential Circuits (cont.) Sequential Logic: Output depends not only on current input but also on past input values Store information between operations Need some type of memory (Register) to remember the past input values. (Commonly use D type Flip Flops as Registers) 3

4 Define Schematic Terminology D(3:0) 4 4 I/Ps O/Ps P (P,Dout(3:0)) Dout(3:0) 5 D(3) Not a short circuit! Signals merge into a Bus or Vector D(2) D(3:0) D(1) D(0) 4

5 Sequential Circuits (cont.) Information Storing Circuits Registers(Flip Flops) Probably more than 1 bit if >2 states Timed States 5

6 Sequential Logic: Concept Sequential Logic circuits remember past inputs and past circuit state. Outputs from the system are fed back as new inputs. The storage elements are circuits that are capable of storing binary information: memory. 6

7 Synchronous vs. Asynchronous machines There are two types of sequential circuits: Synchronous sequential circuit: the behavior can be defined from knowledge of its signal at discrete instants of time. This type of circuits achieves synchronization by using a timing signal called the clock. Asynchronous (fundamental mode) sequential circuit: the behavior is dependent on the order of input signal changes over continuous time, and output can change at any time (clockless). 7

8 Clock Signal Rising Clock Edge Clock generator: Periodic train of clock pulses Different duty cycles Falling Clock Edge 8

9 Circuits: Flip flops as state memory The flip-flops flops receive their inputs from the combinational circuit and also from a clock signal with edges (rising or falling) that occur at fixed intervals of time, as shown in the timing diagram. 9

10 Storing Elements Buffers Can t change the stored value! Inverters 10

11 SR latch (NOR version) -- SR: set-reset, bistable element with two extra inputs; note the undefined output for S=R=1. -- Reading the logic: Q = (R+Q ) ; P = (S+Q) Illegal state 11

12 R=S=1?? Illegal output, because When S=R=1, both outputs go to zero. If both inputs now go to 0, the state of the SR flip flop is depends on which input remains a 1 longer before making transition to 0. Hence, undefined state. MUST be avoided.

13 S R Latch (NAND version) 0 1 S R Q Q 1 0 S R Q Q Set X Y NAND

14 S R Latch (NAND version) 1 1 S R Q Q 1 0 S R Q Q Set 1 0 Hold X Y NAND

15 S R Latch (NAND version) 1 0 S R Q Q 0 1 S R Q Q Set 0 1 Reset 1 0 Hold X Y NAND

16 S R Latch (NAND version) 1 1 S R Q Q 0 1 X Y NAND S R Q Q Set 0 1 Reset 1 0 Hold 0 1 Hold 16

17 S R Latch (NAND version) 0 0 S R Q Q 1 1 X Y NAND S R Q Q Disallowed Set Reset Hold 0 1 Hold 17

18 SR Latches 18

19 SR Latch Simulation (Timing Diagram) 19

20 SR Latch with Clock signal Latch is sensitive to input changes ONLY when C=1 20

21 SR Latch with Clock signal S R (cont.) S R Q Q S R S R Q Q Q 0 Q 0 Store Reset Set Disallowed X X Q 0 Q 0 Store 21

22 D Latch One way to eliminate the undesirable indeterminate state in the RS flip flop is to ensure that inputs S and R are never 1 simultaneously. This is done in the D latch: 22

23 D Latch (cont.) D S S Q R R Q D Q Q X 0 Q 0 Q 0 S R Q Q Q 0 Q 0 Store Reset Set Disallowed X X 0 Q 0 Q 0 Store 23

24 Latches: Behaviour & Issues Level triggered Latches are transparent (= any change on the inputs is seen at the outputs immediately). This causes synchronization problems! (not recommended for use in synchronous designs) Solution: use latches to create flip-flops that can respond (update) ONLY on SPECIFIC times (instead of ANY time). 24

25 Alternatives in FF choice Edge triggered (rising or falling edge of clk) used in synchronous design Various types exist: RS D JK 25

26 SR Flip Flop Master Slave Enables edge-triggered behavior This is NOT a latch (even though it is built from latches 26

27 SR Flip Flop (contd.) S R Q Q 0 0 Q 0 Q 0 Store Reset Set Disallowed X X 0 Q 0 Q 0 Store When C=1, master is enabled and stores new data, slave stores old data. When C=0, master s state passes to enabled slave (Q=Y), master not sensitive to new data (disabled). 27

28 Master-Slave J-K Flip-Flop 28

29 Flops Attach level-triggered D latch to level-triggered SR latch, using complemented clocks. D-Type Positive Edge-Triggered Flip-Flop: Positive Edge-triggered D Flip- 29

30 Positive Edge-Triggered J-K Flip-Flop 30