How To Time A Clock On A Clock (Clock)
|
|
|
- Buck Kelly
- 3 years ago
- Views:
Transcription
1 Chapter 5 Flip-Flops, Registers, and Counters
2 Sensor Reset Set Memory element On Off Alarm Figure 5.1. Control of an alarm system.
3 A B Figure 5.2. A simple memory element.
4 Reset Set Figure 5.3. A memory element with NOR gates.
5 R a S R a b /1 1/ (no change) S b 1 1 (a) Circuit (b) Truth table t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 R S a b ?? Time (c) Timing diagram Figure 5.4. A basic latch built with NOR gates.
6 Please see portrait orientation PowerPoint file for Chapter 5 Figure 5.5. Gated SR latch.
7 S Clk R Figure 5.6. Gated SR latch with NAND gates.
8 Please see portrait orientation PowerPoint file for Chapter 5 Figure 5.7. Gated D latch.
9 t su t h Clk D Figure 5.8. Setup and hold times.
10 Please see portrait orientation PowerPoint file for Chapter 5 Figure 5.9. Master-slave D flip-flop.
11 Please see portrait orientation PowerPoint file for Chapter 5 Figure 5.1. Comparison of level-sensitive and edge-triggered D storage elements.
12 1 P3 2 P1 5 Clock 3 P2 6 D D 4 P4 Clock (a) Circuit (b) Graphical symbol Figure A positive-edge-triggered D flip-flop.
13 Figure Master-slave D flip-flop with Clear and Preset.
14 Please see portrait orientation PowerPoint file for Chapter 5 Figure Positive-edge-triggered D flip-flop with and Preset. Clear
15 Figure Timing for a flip-flop.
16 Please see portrait orientation PowerPoint file for Chapter 5 Figure T flip-flop.
17 J D K Clock (a) Circuit J 1 1 K 1 ( t + 1) ( t) 1 1 ( t) J K (b) Truth table (c) Graphical symbol Figure JK flip-flop.
18 In D D D D Out Clock (a) Circuit t In = Out t 1 1 t t t t t t (b) A sample sequence Figure A simple shift register.
19 Figure Parallel-access shift register.
20 1 T T T Clock 1 2 (a) Circuit Clock 1 2 Count (b) Timing diagram Figure A three-bit up-counter.
21 1 T T T Clock 1 2 (a) Circuit Clock 1 2 Count (b) Timing diagram Figure 5.2. A three-bit down-counter.
22 Clock cycle changes 2 changes Table 5.1. Derivation of the synchronous up-counter.
23 1 T T T 1 2 T 3 Clock (a) Circuit Clock Count (b) Timing diagram Figure A four-bit synchronous up-counter.
24 Enable T T T T Clock Clear_n Figure Inclusion of Enable and Clear capability.
25 Please see portrait orientation PowerPoint file for Chapter 5 Figure A four-bit counter with D flip-flops.
26 Please see portrait orientation PowerPoint file for Chapter 5 Figure A counter with parallel-load capability.
27 1 Enable D D 1 1 Clock D 2 Load Clock 2 (a) Circuit Clock 1 2 Count (b) Timing diagram Figure A modulo-6 counter with synchronous reset.
28 1 T T T 1 2 Clock (a) Circuit Clock 1 2 Count (b) Timing diagram Figure A modulo-6 counter with asynchronous reset.
29 Figure A two-digit BCD counter.
30 Please see portrait orientation PowerPoint file for Chapter 5 Figure Ring counter.
31 Figure Johnson counter.
32 Figure 5.3. Three types of storage elements in a schematic.
33 Data Clock Latch Figure Gated D latch generated by CAD tools.
34 Please see portrait orientation PowerPoint file for Chapter 5 Figure Implementation of the schematic in Figure 5.3 in a CPLD.
35 Figure Timing simulation of storage elements in Figure 5.3.
36 module D_latch (D, Clk, ); input D, Clk; output reg ; Clk) if (Clk) = D; endmodule Figure Code for a gated D latch.
37 module flipflop (D, Clock, ); input D, Clock; output reg ; Clock) = D; endmodule Figure Code for a D flip-flop.
38 module example5_3 (D, Clock, 1, 2); input D, Clock; output reg 1, 2; Clock) begin 1 = D; 2 = 1; end endmodule Figure Incorrect code for two cascaded flip-flops.
39 D D 1 Clock D 2 Figure Circuit for Example 5.3.
40 module example5_4 (D, Clock, 1, 2); input D, Clock; output reg 1, 2; Clock) begin 1 <= D; 2 <= 1; end endmodule Figure Code for two cascaded flip-flops.
41 D D 1 2 D Clock Figure Circuit defined in Figure 5.38.
42 module example5_5 (x1, x2, x3, Clock, f, g); input x1, x2, x3, Clock; output reg f, g; Clock) begin f = x1 & x2; g = f x3; end endmodule Figure 5.4. Code for Example 5.5.
43 x 3 x 1 D g x 2 D f Clock Figure Circuit for Example 5.5.
44 module example5_6 (x1, x2, x3, Clock, f, g); input x1, x2, x3, Clock; output reg f, g; Clock) begin f <= x1 & x2; g <= f x3; end endmodule Figure Code for Example 5.6.
45 x 3 D g x 1 x 2 D f Clock Figure Circuit for Example 5.6.
46 module flipflop (D, Clock, Resetn, ); input D, Clock, Resetn; output reg ; Resetn, posedge Clock) if (!Resetn) <= ; else <= D; endmodule Figure D flip-flop with asynchronous reset.
47 module flipflop (D, Clock, Resetn, ); input D, Clock, Resetn; output reg ; Clock) if (!Resetn) <= ; else <= D; endmodule Figure D flip-flop with synchronous reset.
48 module regn (D, Clock, Resetn, ); parameter n = 16; input [n-1:] D; input Clock, Resetn; output reg [n-1:] ; Resetn, posedge Clock) if (!Resetn) <= ; else <= D; endmodule Figure Code for an n-bit register with asynchronous clear.
49 module muxdff (D, D1, Sel, Clock, ); input D, D1, Sel, Clock; output reg ; Clock) if (!Sel) <= D; else <= D1; endmodule Figure Code for a D flip-flop with a 2-to-1 multiplexer on the D input.
50 module muxdff (D, D1, Sel, Clock, ); input D, D1, Sel, Clock; output reg ;! wire D; assign D = Sel? D1 : D;! Clock) <= D; endmodule Figure Alternative code for a D flip-flop with a 2-to-1 multiplexer on the D input.
51 module shift4 (R, L, w, Clock, ); input [3:] R; input L, w, Clock; output [3:] ; wire [3:] ; muxdff Stage3 (w, R[3], L, Clock, [3]); muxdff Stage2 ([3], R[2], L, Clock, [2]); muxdff Stage1 ([2], R[1], L, Clock, [1]); muxdff Stage ([1], R[], L, Clock, []); endmodule Figure Hierarchical code for a four-bit shift register.
52 module shift4 (R, L, w, Clock, ); input [3:] R; input L, w, Clock; output reg [3:] ; Clock) if (L) <= R; else begin [] <= [1]; [1] <= [2]; [2] <= [3]; [3] <= w; end endmodule Figure 5.5. Alternative code for a four-bit shift register.
53 module shiftn (R, L, w, Clock, ); parameter n = 16; input [n-1:] R; input L, w, Clock; output reg [n-1:] ; integer k; Clock) if (L) <= R; else begin for (k = ; k < n-1; k = k+1) [k] <= [k+1]; [n-1] <= w; end endmodule Figure An n-bit shift register.
54 module upcount (Resetn, Clock, E, ); input Resetn, Clock, E; output reg [3:] ; Resetn, posedge Clock) if (!Resetn) <= ; else if (E) <= + 1; endmodule Figure Code for a four-bit up-counter.
55 module upcount (R, Resetn, Clock, E, L, ); input [3:] R; input Resetn, Clock, E, L; output reg [3:] ; Resetn, posedge Clock) if (!Resetn) <= ; else if (L) <= R; else if (E) <= + 1; endmodule Figure A four-bit up-counter with parallel load.
56 module downcount (R, Clock, E, L, ); parameter n = 8; input [n-1:] R; input Clock, L, E; output reg [n-1:] ; Clock) if (L) <= R; else if (E) <= - 1; endmodule Figure A down-counter with a parallel load.
57 module updowncount (R, Clock, L, E, up_down, ); parameter n = 8; input [n-1:] R; input Clock, L, E, up_down; output reg [n-1:] ; Clock) if (L) <= R; else if (E) <= + (up_down? 1 : -1); endmodule Figure Code for an up/down counter.
58 Figure Providing an enable input for a D flip-flop.
59 module rege (D, Clock, Resetn, E, ); input D, Clock, Resetn, E; output reg ; Clock, negedge Resetn) if (Resetn == ) <= ; else if (E) <= D; endmodule Figure Code for a D flip-flop with enable.
60 module regne (R, Clock, Resetn, E, ); parameter n = 8; input [n-1:] R; input Clock, Resetn, E; output reg [n-1:] ; Clock, negedge Resetn) if (Resetn == ) <= ; else if (E) <= R; endmodule Figure An n-bit register with an enable input.
61 Figure A shift register with parallel load and enable control inputs.
62 module shiftrne (R, L, E, w, Clock, ); parameter n = 4; input [n-1:] R; input L, E, w, Clock; output reg [n-1:] ; integer k; Clock) begin if (L) <= R; else if (E) begin [n-1] <= w; for (k = n-2; k >= ; k = k-1) [k] <= [k+1]; end end endmodule Figure 5.6. A left-to-right shift register with an enable input.
63 Please see portrait orientation PowerPoint file for Chapter 5 Figure A reaction-timer circuit.
64 Please see portrait orientation PowerPoint file for Chapter 5 Figure Code for the two-digit BCD counter in Figure 5.27.
65 Figure Code for the BCD-to-7-segment decoder.
66 Figure Code for the reaction timer.
67 Figure Simulation of the reaction-timer circuit.
68 Figure A simple flip-flop circuit.
69 Please see portrait orientation PowerPoint file for Chapter 5 Figure A 4-bit counter.
70 Figure A general example of clock skew.
71 Figure A modified version of the reaction-timer circuit.
72 Figure 5.7. Circuit for Example 5.18.
73 Figure Circuit for Example 5.19.
74 Figure Summary of the behavior of the circuit in Figure 5.71.
75 Please see portrait orientation PowerPoint file for Chapter 5 Figure Circuit for Example 5.2.
76 module vend (N, D,, Resetn, Coin, Z); input N, D,, Resetn, Coin; output Z; wire [4:] X; reg [5:] S;! assign X[] = N ; assign X[1] = D; assign X[2] = N; assign X[3] = D ; assign X[4] = ; assign Z = S[5] (S[4] & S[3] & S[2] & S[1]); Coin, negedge Resetn) if (Resetn = = 1 b) S <= 5 b; else S <= {1 b, X} + S; end endmodule Figure Code for Example 5.21.
77 Please see portrait orientation PowerPoint file for Chapter 5 Figure A faster 4-bit counter.
78 Figure A circuit with clock skews.
79 Clock D Figure P5.1. Timing diagram for Problem 5.1.
80 Figure P5.2. Circuit for Problem 5.8.
81 1 2 1 T T T Clock Figure P5.3. The circuit for Problem 5.17.
82 J S S Clock Clk Clk K R R Figure P5.4. Circuit for Problem 5.18.
83 Figure P5.5. A ring oscillator. f
84 Reset Interval 1 ns Figure P5.6. Timing of signals for Problem 5.24.
85 D Clock A Clock D A Figure P5.7. Circuit and timing diagram for Problem 5.25.
86 Clock Start f g Figure P5.8. Timing diagram for Problem 5.26.
87 module lfsr (R, L, Clock, ); input [:2] R; input L, Clock; output reg [:2] ; Clock) if (L) <= R; else <= {[2], [] ^ [2], [1]}; endmodule Figure P5.9. Code for a linear-feedback shift register.
88 module lfsr (R, L, Clock, ); input [:2] R; input L, Clock; output reg [:2] ; Clock) if (L) <= R; else <= {[2], [], [1] ^ [2]}; endmodule Figure P5.1. Code for a linear-feedback shift register.
89 module lfsr (R, L, Clock, ); input [:2] R; input L, Clock; output reg [:2] ; Clock) if (L) <= R; else begin [] = [2]; [1] = [] ^ [2]; [2] = [1]; end endmodule Figure P5.11. Code for Problem 7.3.
90 module lfsr (R, L, Clock, ); input [:2] R; input L, Clock; output reg [:2] ; Clock) if (L) <= R; else begin [] = [2]; [1] = []; [2] = [1] ^ [2]; end endmodule Figure P5.12. Code for Problem 5.31.
Flip-Flops, Registers, Counters, and a Simple Processor
June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 Flip-Flops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number
Modeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit
Modeling Sequential Elements with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 4-1 Sequential Circuit Outputs are functions of inputs and present states of storage elements
Registers & Counters
Objectives This section deals with some simple and useful sequential circuits. Its objectives are to: Introduce registers as multi-bit storage devices. Introduce counters by adding logic to registers implementing
Engr354: Digital Logic Circuits
Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flip-flops;
Module 3: Floyd, Digital Fundamental
Module 3: Lecturer : Yongsheng Gao Room : Tech - 3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental
Latches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012
Latches, the D Flip-Flop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR
Memory Elements. Combinational logic cannot remember
Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic
WEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1
WEEK 8.1 egisters and Counters ECE124 igital Circuits and Systems Page 1 Additional schematic FF symbols Active low set and reset signals. S Active high set and reset signals. S ECE124 igital Circuits
ECE380 Digital Logic
ECE38 igital Logic Flip-Flops, Registers and Counters: Flip-Flops r.. J. Jackson Lecture 25- Flip-flops The gated latch circuits presented are level sensitive and can change states more than once during
CHAPTER 11 LATCHES AND FLIP-FLOPS
CHAPTER 11 LATCHES AND FLIP-FLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop
Modeling Registers and Counters
Lab Workbook Introduction When several flip-flops are grouped together, with a common clock, to hold related information the resulting circuit is called a register. Just like flip-flops, registers may
Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa
Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation
CDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012
CDA 3200 Digital Systems Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012 Outline SR Latch D Latch Edge-Triggered D Flip-Flop (FF) S-R Flip-Flop (FF) J-K Flip-Flop (FF) T Flip-Flop
Counters & Shift Registers Chapter 8 of R.P Jain
Chapter 3 Counters & Shift Registers Chapter 8 of R.P Jain Counters & Shift Registers Counters, Syllabus Design of Modulo-N ripple counter, Up-Down counter, design of synchronous counters with and without
Flip-Flops and Sequential Circuit Design. ECE 152A Winter 2012
Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6
Flip-Flops and Sequential Circuit Design
Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6
Asynchronous Counters. Asynchronous Counters
Counters and State Machine Design November 25 Asynchronous Counters ENGI 25 ELEC 24 Asynchronous Counters The term Asynchronous refers to events that do not occur at the same time With respect to counter
Chapter 7. Registers & Register Transfers. J.J. Shann. J. J. Shann
Chapter 7 Registers & Register Transfers J. J. Shann J.J. Shann Chapter Overview 7- Registers and Load Enable 7-2 Register Transfers 7-3 Register Transfer Operations 7-4 A Note for VHDL and Verilog Users
Sequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements )
Sequential Logic (Materials taken from: Principles of Computer Hardware by Alan Clements ) Sequential vs. Combinational Circuits Combinatorial circuits: their outputs are computed entirely from their present
LAB #4 Sequential Logic, Latches, Flip-Flops, Shift Registers, and Counters
LAB #4 Sequential Logic, Latches, Flip-Flops, Shift Registers, and Counters LAB OBJECTIVES 1. Introduction to latches and the D type flip-flop 2. Use of actual flip-flops to help you understand sequential
Chapter 5. Sequential Logic
Chapter 5 Sequential Logic Sequential Circuits (/2) Combinational circuits: a. contain no memory elements b. the outputs depends on the current inputs Sequential circuits: a feedback path outputs depends
Sequential Logic Design Principles.Latches and Flip-Flops
Sequential Logic Design Principles.Latches and Flip-Flops Doru Todinca Department of Computers Politehnica University of Timisoara Outline Introduction Bistable Elements Latches and Flip-Flops S-R Latch
ECE232: Hardware Organization and Design. Part 3: Verilog Tutorial. http://www.ecs.umass.edu/ece/ece232/ Basic Verilog
ECE232: Hardware Organization and Design Part 3: Verilog Tutorial http://www.ecs.umass.edu/ece/ece232/ Basic Verilog module ();
Chapter 9 Latches, Flip-Flops, and Timers
ETEC 23 Programmable Logic Devices Chapter 9 Latches, Flip-Flops, and Timers Shawnee State University Department of Industrial and Engineering Technologies Copyright 27 by Janna B. Gallaher Latches A temporary
Digital Logic Design Sequential circuits
Digital Logic Design Sequential circuits Dr. Eng. Ahmed H. Madian E-mail: ahmed.madian@guc.edu.eg Dr. Eng. Rania.Swief E-mail: rania.swief@guc.edu.eg Dr. Eng. Ahmed H. Madian Registers An n-bit register
Master/Slave Flip Flops
Master/Slave Flip Flops Page 1 A Master/Slave Flip Flop ( Type) Gated latch(master) Gated latch (slave) 1 Gate Gate GATE Either: The master is loading (the master in on) or The slave is loading (the slave
Chapter 8. Sequential Circuits for Registers and Counters
Chapter 8 Sequential Circuits for Registers and Counters Lesson 3 COUNTERS Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline Counters T-FF Basic Counting element State
To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC.
8.1 Objectives To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC. 8.2 Introduction Circuits for counting events are frequently used in computers and other digital
Copyright Peter R. Rony 2009. All rights reserved.
Experiment No. 1. THE DIGI DESIGNER Experiment 1-1. Socket Connections on the Digi Designer Experiment No. 2. LOGIC LEVELS AND THE 7400 QUADRUPLE 2-INPUT POSITIVE NAND GATE Experiment 2-1. Truth Table
Design Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters:
Design Eample: ers er: a sequential circuit that repeats a specified sequence of output upon clock pulses. A,B,C,, Z. G, O, T, E, R, P, S,!.,,,,,,,7. 7,,,,,,,.,,,,,,,,,,,. Binary counter: follows the binary
DIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department
Counters By: Electrical Engineering Department 1 Counters Upon completion of the chapter, students should be able to:.1 Understand the basic concepts of asynchronous counter and synchronous counters, and
Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill
Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Objectives: Analyze the operation of sequential logic circuits. Understand the operation of digital counters.
ETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies
ETEC 2301 Programmable Logic Devices Chapter 10 Counters Shawnee State University Department of Industrial and Engineering Technologies Copyright 2007 by Janna B. Gallaher Asynchronous Counter Operation
Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng
Digital Logic Design Basics Combinational Circuits Sequential Circuits Pu-Jen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction
DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute. 2nd (Spring) term 2012/2013
DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 4. LECTURE: COUNTERS AND RELATED 2nd (Spring) term 2012/2013 1 4. LECTURE: COUNTERS AND RELATED 1. Counters,
Timing Methodologies (cont d) Registers. Typical timing specifications. Synchronous System Model. Short Paths. System Clock Frequency
Registers Timing Methodologies (cont d) Sample data using clock Hold data between clock cycles Computation (and delay) occurs between registers efinition of terms setup time: minimum time before the clocking
DATA SHEETS DE COMPONENTES DA FAMÍLIA LÓGICA TTL GATES AND INVERTERS POSITIVES NAND GATES AND INVERTERS DESCRIÇÃO
GATES AND INVERTERS POSITIVES NAND GATES AND INVERTERS Hex Invertes 74LS04 Quadruple 2 Inputs Gates 74LS00 Triple 3 Inputs Gates 74LS10 Dual 4 Inputs Gates 74LS20 8 Inputs Gates 74LS30 13 Inputs Gates
More Verilog. 8-bit Register with Synchronous Reset. Shift Register Example. N-bit Register with Asynchronous Reset.
More Verilog 8-bit Register with Synchronous Reset module reg8 (reset, CLK, D, Q); input reset; input [7:0] D; output [7:0] Q; reg [7:0] Q; if (reset) Q = 0; else Q = D; module // reg8 Verilog - 1 Verilog
Contents COUNTER. Unit III- Counters
COUNTER Contents COUNTER...1 Frequency Division...2 Divide-by-2 Counter... 3 Toggle Flip-Flop...3 Frequency Division using Toggle Flip-flops...5 Truth Table for a 3-bit Asynchronous Up Counter...6 Modulo
Combinational Logic Design Process
Combinational Logic Design Process Create truth table from specification Generate K-maps & obtain logic equations Draw logic diagram (sharing common gates) Simulate circuit for design verification Debug
Counters are sequential circuits which "count" through a specific state sequence.
Counters Counters are sequential circuits which "count" through a specific state sequence. They can count up, count down, or count through other fixed sequences. Two distinct types are in common usage:
Lecture 8: Synchronous Digital Systems
Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered
Chapter 7: Advanced Modeling Techniques
Chapter 7: Advanced Modeling Techniques Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog HDL
Lab #5: Design Example: Keypad Scanner and Encoder - Part 1 (120 pts)
Dr. Greg Tumbush, gtumbush@uccs.edu Lab #5: Design Example: Keypad Scanner and Encoder - Part 1 (120 pts) Objective The objective of lab assignments 5 through 9 are to systematically design and implement
EXPERIMENT 8. Flip-Flops and Sequential Circuits
EXPERIMENT 8. Flip-Flops and Sequential Circuits I. Introduction I.a. Objectives The objective of this experiment is to become familiar with the basic operational principles of flip-flops and counters.
Standart TTL, Serie 74... Art.Gruppe 13.15. 1...
Standart TTL, Serie 74... Art.Gruppe 13.15. 1... Standart TTL, Serie 74... 7400 Quad 2-Input Nand Gate (TP) DIL14 7402 Quad 2 Input Nor Gate (TP) DIL14 7403 Quad 2 Input Nand Gate (OC) DIL14 7404 Hex Inverter
Design Verification & Testing Design for Testability and Scan
Overview esign for testability (FT) makes it possible to: Assure the detection of all faults in a circuit Reduce the cost and time associated with test development Reduce the execution time of performing
Lesson 12 Sequential Circuits: Flip-Flops
Lesson 12 Sequential Circuits: Flip-Flops 1. Overview of a Synchronous Sequential Circuit We saw from last lesson that the level sensitive latches could cause instability in a sequential system. This instability
BINARY CODED DECIMAL: B.C.D.
BINARY CODED DECIMAL: B.C.D. ANOTHER METHOD TO REPRESENT DECIMAL NUMBERS USEFUL BECAUSE MANY DIGITAL DEVICES PROCESS + DISPLAY NUMBERS IN TENS IN BCD EACH NUMBER IS DEFINED BY A BINARY CODE OF 4 BITS.
DIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse.
DIGITAL COUNTERS http://www.tutorialspoint.com/computer_logical_organization/digital_counters.htm Copyright tutorialspoint.com Counter is a sequential circuit. A digital circuit which is used for a counting
Fundamentals of Digital Electronics
Fundamentals of Digital Electronics by Professor Barry Paton Dalhousie University March 998 Edition Part Number 32948A- Fundamentals of Digital Electronics Copyright Copyright 998 by National Instruments
Counters and Decoders
Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4-bit ripple-through decade counter with a decimal read-out display. Such a counter
CHAPTER IX REGISTER BLOCKS COUNTERS, SHIFT, AND ROTATE REGISTERS
CHAPTER IX-1 CHAPTER IX CHAPTER IX COUNTERS, SHIFT, AN ROTATE REGISTERS REA PAGES 249-275 FROM MANO AN KIME CHAPTER IX-2 INTROUCTION -INTROUCTION Like combinational building blocks, we can also develop
7. Latches and Flip-Flops
Chapter 7 Latches and Flip-Flops Page 1 of 18 7. Latches and Flip-Flops Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can store one bit of information. The
Counters. Present State Next State A B A B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0
ounter ounters ounters are a specific type of sequential circuit. Like registers, the state, or the flip-flop values themselves, serves as the output. The output value increases by one on each clock cycle.
Theory of Logic Circuits. Laboratory manual. Exercise 3
Zakład Mikroinformatyki i Teorii Automatów yfrowych Theory of Logic ircuits Laboratory manual Exercise 3 Bistable devices 2008 Krzysztof yran, Piotr zekalski (edt.) 1. lassification of bistable devices
L4: Sequential Building Blocks (Flip-flops, Latches and Registers)
L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Prof. Randy Katz (Unified
CSE140: Components and Design Techniques for Digital Systems
CE4: Components and esign Techniques for igital ystems Tajana imunic osing ources: Where we are now What we ve covered so far (Chap -5, App. A& B) Number representations Boolean algebra OP and PO Logic
ECE 451 Verilog Exercises. Sept 14, 2007. James Barnes (James.Barnes@colostate.edu)
ECE 451 Verilog Exercises Sept 14, 2007 James Barnes (James.Barnes@colostate.edu) Organization These slides give a series of self-paced exercises. Read the specification of each exercise and write your
Modeling Latches and Flip-flops
Lab Workbook Introduction Sequential circuits are digital circuits in which the output depends not only on the present input (like combinatorial circuits), but also on the past sequence of inputs. In effect,
CHAPTER 3 Boolean Algebra and Digital Logic
CHAPTER 3 Boolean Algebra and Digital Logic 3.1 Introduction 121 3.2 Boolean Algebra 122 3.2.1 Boolean Expressions 123 3.2.2 Boolean Identities 124 3.2.3 Simplification of Boolean Expressions 126 3.2.4
Cascaded Counters. Page 1 BYU
Cascaded Counters Page 1 Mod-N Counters Generally we are interested in counters that count up to specific count values Not just powers of 2 A mod-n counter has N states Counts from 0 to N-1 then rolls
Sequential Logic: Clocks, Registers, etc.
ENEE 245: igital Circuits & Systems Lab Lab 2 : Clocks, Registers, etc. ENEE 245: igital Circuits and Systems Laboratory Lab 2 Objectives The objectives of this laboratory are the following: To design
Upon completion of unit 1.1, students will be able to
Upon completion of unit 1.1, students will be able to 1. Demonstrate safety of the individual, class, and overall environment of the classroom/laboratory, and understand that electricity, even at the nominal
DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 5. LECTURE: REGISTERS AND RELATED
DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 5. LECTURE: REGISTERS AND RELATED 2nd (Spring) term 22/23 5. LECTURE: REGISTERS. Storage registers 2. Shift
DM74LS169A Synchronous 4-Bit Up/Down Binary Counter
Synchronous 4-Bit Up/Down Binary Counter General Description This synchronous presettable counter features an internal carry look-ahead for cascading in high-speed counting applications. Synchronous operation
SEQUENTIAL CIRCUITS. Block diagram. Flip Flop. S-R Flip Flop. Block Diagram. Circuit Diagram
SEQUENTIAL CIRCUITS http://www.tutorialspoint.com/computer_logical_organization/sequential_circuits.htm Copyright tutorialspoint.com The combinational circuit does not use any memory. Hence the previous
Layout of Multiple Cells
Layout of Multiple Cells Beyond the primitive tier primitives add instances of primitives add additional transistors if necessary add substrate/well contacts (plugs) add additional polygons where needed
Lecture 12: More on Registers, Multiplexers, Decoders, Comparators and Wot- Nots
Lecture 12: More on Registers, Multiplexers, Decoders, Comparators and Wot- Nots Registers As you probably know (if you don t then you should consider changing your course), data processing is usually
Digital Fundamentals
igital Fundamentals with PL Programming Floyd Chapter 9 Floyd, igital Fundamentals, 10 th ed, Upper Saddle River, NJ 07458. All Rights Reserved Summary Latches (biestables) A latch is a temporary storage
EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/20 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,
Lecture-3 MEMORY: Development of Memory:
Lecture-3 MEMORY: It is a storage device. It stores program data and the results. There are two kind of memories; semiconductor memories & magnetic memories. Semiconductor memories are faster, smaller,
74LS193 Synchronous 4-Bit Binary Counter with Dual Clock
74LS193 Synchronous 4-Bit Binary Counter with Dual Clock General Description The DM74LS193 circuit is a synchronous up/down 4-bit binary counter. Synchronous operation is provided by having all flip-flops
CS311 Lecture: Sequential Circuits
CS311 Lecture: Sequential Circuits Last revised 8/15/2007 Objectives: 1. To introduce asynchronous and synchronous flip-flops (latches and pulsetriggered, plus asynchronous preset/clear) 2. To introduce
CpE358/CS381. Switching Theory and Logical Design. Class 10
CpE358/CS38 Switching Theory and Logical Design Class CpE358/CS38 Summer- 24 Copyright 24-373 Today Fundamental concepts of digital systems (Mano Chapter ) Binary codes, number systems, and arithmetic
DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control
August 1986 Revised February 1999 DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control General Description The DM74LS191 circuit is a synchronous, reversible, up/ down counter. Synchronous operation
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.
PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS The SN54/74LS90 is a synchronous UP/DOWN BCD Decade (842) Counter and the SN54/74LS9 is a synchronous UP/DOWN Modulo-6
Fig1-1 2-bit asynchronous counter
Digital electronics 1-Sequential circuit counters Such a group of flip- flops is a counter. The number of flip-flops used and the way in which they are connected determine the number of states and also
Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.
Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage
INTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic
DM54161 DM74161 DM74163 Synchronous 4-Bit Counters
DM54161 DM74161 DM74163 Synchronous 4-Bit Counters General Description These synchronous presettable counters feature an internal carry look-ahead for application in high-speed counting designs The 161
Digital Electronics Detailed Outline
Digital Electronics Detailed Outline Unit 1: Fundamentals of Analog and Digital Electronics (32 Total Days) Lesson 1.1: Foundations and the Board Game Counter (9 days) 1. Safety is an important concept
Digital Circuit Design Using Xilinx ISE Tools
Digital Circuit Design Using Xilinx ISE Tools Contents 1. Introduction... 1 2. Programmable Logic Device: FPGA... 2 3. Creating a New Project... 2 4. Synthesis and Implementation of the Design... 11 5.
Gray Code Generator and Decoder by Carsten Kristiansen Napier University. November 2004
Gray Code Generator and Decoder by Carsten Kristiansen Napier University November 2004 Title page Author: Carsten Kristiansen. Napier No: 04007712. Assignment title: Design of a Gray Code Generator and
IE1204 Digital Design F12: Asynchronous Sequential Circuits (Part 1)
IE1204 Digital Design F12: Asynchronous Sequential Circuits (Part 1) Elena Dubrova KTH / ICT / ES dubrova@kth.se BV pp. 584-640 This lecture IE1204 Digital Design, HT14 2 Asynchronous Sequential Machines
LOGICOS SERIE 4000. Precios sujetos a variación. Ref. Part # Descripción Precio Foto Ref. Quad 2-Input NOR Buffered B Series Gate / PDIP-14
LOGICOS SERIE 4000 Precios sujetos a variación Ref. Part # Descripción Precio Foto Ref. A-6-1 CD4001 Quad 2-Input NOR Buffered B Series Gate / PDIP-14 $ 290 A-6-2 CD4001BCM Quad 2-Input NOR Buffered B
A Lesson on Digital Clocks, One Shots and Counters
A Lesson on Digital Clocks, One Shots and Counters Topics Clocks & Oscillators LM 555 Timer IC Crystal Oscillators Selection of Variable Resistors Schmitt Gates Power-On Reset Circuits One Shots Counters
E158 Intro to CMOS VLSI Design. Alarm Clock
E158 Intro to CMOS VLSI Design Alarm Clock Sarah Yi & Samuel (Tae) Lee 4/19/2010 Introduction The Alarm Clock chip includes the basic functions of an alarm clock such as a running clock time and alarm
Asynchronous counters, except for the first block, work independently from a system clock.
Counters Some digital circuits are designed for the purpose of counting and this is when counters become useful. Counters are made with flip-flops, they can be asynchronous or synchronous and they can
路 論 Chapter 15 System-Level Physical Design
Introduction to VLSI Circuits and Systems 路 論 Chapter 15 System-Level Physical Design Dept. of Electronic Engineering National Chin-Yi University of Technology Fall 2007 Outline Clocked Flip-flops CMOS
A Lesson on Digital Clocks, One Shots and Counters
A Lesson on Digital Clocks, One Shots and Counters Topics Clocks & Oscillators LM 555 Timer IC Crystal Oscillators Selection of Variable Resistors Schmitt Gates Power-On Reset Circuits One Shots Counters
The components. E3: Digital electronics. Goals:
E3: Digital electronics Goals: Basic understanding of logic circuits. Become familiar with the most common digital components and their use. Equipment: 1 st. LED bridge 1 st. 7-segment display. 2 st. IC
DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock
September 1986 Revised March 2000 DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock General Description The DM74LS193 circuit is a synchronous up/down 4-bit binary counter. Synchronous operation
A Verilog HDL Test Bench Primer Application Note
A Verilog HDL Test Bench Primer Application Note Table of Contents Introduction...1 Overview...1 The Device Under Test (D.U.T.)...1 The Test Bench...1 Instantiations...2 Figure 1- DUT Instantiation...2
Digital Electronics Part I Combinational and Sequential Logic. Dr. I. J. Wassell
Digital Electronics Part I Combinational and Sequential Logic Dr. I. J. Wassell Introduction Aims To familiarise students with Combinational logic circuits Sequential logic circuits How digital logic gates
Fig 3. PLC Relay Output
1. Function of a PLC PLC Basics A PLC is a microprocessor-based controller with multiple inputs and outputs. It uses a programmable memory to store instructions and carry out functions to control machines
Systems I: Computer Organization and Architecture
Systems I: omputer Organization and Architecture Lecture 8: Registers and ounters Registers A register is a group of flip-flops. Each flip-flop stores one bit of data; n flip-flops are required to store
Life Cycle of a Memory Request. Ring Example: 2 requests for lock 17
Life Cycle of a Memory Request (1) Use AQR or AQW to place address in AQ (2) If A[31]==0, check for hit in DCache Ring (3) Read Hit: place cache word in RQ; Write Hit: replace cache word with WQ RDDest/RDreturn
Sequential Circuit Design
Sequential Circuit Design Lan-Da Van ( 倫 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2009 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines