The FET Constant-Current Source/Limiter. I D = ( V DS )(g oss ) (3) R L. g oss. where g oss = g oss (5) when V GS = 0 (6)

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1 The FET Constant-Current ource/limiter Introduction The combination of low associated operating voltage and high output impedance makes the FET attractive as a constant-current source. An adjustable-current source (Figure ) may be built with a FET, a variable resistor, and a small battery. For optimum thermal stability, the FET should be biased near the zero temperature coefficient point. R R L A change in supply voltage or a change in load impedance, will change I by only a small factor because of the low output conductance g oss. I = (V )(g oss ) (3) The value of g oss is an important consideration in the accuracy of a constant-current source where the supply voltage may vary. As g oss may range from less than to more than 0 according to the FET type, the dynamic impedance can be greater than M to less than 20 k. This corresponds to a current stability range of A to 0 A per volt. The value of g oss also depends on the operating point. Output conductance g oss decrease approximately linearly with I. The relationship is I I g oss g oss (4) NO TAG Figure. Field-Effect Transistor Current ource where g oss = g oss () Whenever the FET is operated in the current saturated region, its output conductance is very low. This occurs whenever the drain-source voltage V is at least 0% greater than the cut-off voltage V G(off). The FET may be biased to operate as a constant-current source at any current below its saturation current I. Basic ource Biasing For a given device where I and V G(off) are known, the approximate V G required for a given I is V G V G(off) I I k () when V G = 0 (6) o as V G V G(off), g oss Zero. For best regulation, I must be considerably less than I. Cascading for Low g oss It is possible to achieve much lower g oss per unit I by cascading two FETs, as shown in Figure 2. Q where k can vary from.8 to 2.0, depending on device geometry. If K = 2.0, the series resistor R required between source and gate is R V G or R I V G(off) I I I (2) Figure 2. R V Cascade FET Current ource R L Updates to this app note may be obtained via facsimile by calling iliconix FaxBack, Please request FaxBack document #7096. iliconix

2 V G2 g fs2 g oss2 Q V 2 (a) I 2 V O I O JFET may have a typical g oss = 4 at V = 20 V and V G = 0. At V V G(off) = 2 V, g oss 00. The best FETs for current sources are those having long gates and consequently very low g oss. The iliconix 2N4340, J202, and T202 exhibit typical g oss = 2 at V = 20 V. These devices in the circuit of Figure 4 will provide a current source adjustable from A to 0.8 ma with internal impedance greater than 2 M at 0.2 ma. Other iliconix part types such as the 2N4392, J2, and T2 can provide 0 ma or higher current. Q 30 V g oss V = V G2 = I O /g oss 200 (Optional) (b) R R = M Figure 3. Cascade FET V G = 0 Now, I is regulated by Q and V = V G2. The dc value of I is controlled by R and Q. However, Q and both affect current stability. The circuit output conductance is derived as follows: If g oss = g oss2 (7) g o g oss 2 g fs goss when R 0 as in Figure 2 g o g oss 2 g fs R g fs (8) (9) In either case (R = 0 or R 0), the circuit output conductance is considerably lower than the g oss of a single FET. In designing any cascaded FET current source, both FETs must be operated with adequate drain-gate voltage, V G. That is, Figure 4. Adjustable Current ource R = M Instead of the adjustable resistor, the JFETs can be put in I range groupings with an appropriate R resistor selected for each group. This method is common in high volume applications. The cascade circuit of Figure provides a current adjustable from 2 A to 0.8 ma with internal resistance greater than 0 M R Q 00 (Optional) 30 V Q = 2N4340, J202, T202 = 2N434, J304, T304 R = M V G V G(off), preferably V G 2V G(off) (0) If V G < 2 V G(off), the g oss will be significantly increased, and circuit g o will deteriorate. For example: A Figure. Cascade FET Current ource 2 iliconix

3 Part Type I F J = T = J00 V F J0 T/J02 T/J03 T/J04 TO-226AA 2-Lead Package TO-236 (OT-23) Package T/J0 CR60 CR80 CR200 CR220 CR240 CR270 TO-8 2-Lead CR300 Package CR330 CR360 CR390 CR430 CR470 T/J06 T/J07 T/J08 T/J09 T/J0 T/J I F Regulator Current (ma) Figure 6. tandard eries Current Regulator Range tandard Two-Leaded evices iliconix offers a special series of two-leaded JFETs with a resistor fabricated on the device, thus creating a 0% current range. evices are available in ranges from.6 ma (CR60) to 4.7 ma (CR470). For designs requiring a 20% current range, iliconix offers devices rated from 0.24 ma typical (J00) through 4.7 ma typical (J) in a two-leaded TO-226A (TO-92) package. The T02 series is available in surface mount TO-236 (OT-23). Each of these two-leaded devices can be used to replace several typical components. Figure 6 shows the current ranges of these two device series. Further information is contained in the individual data sheets appearing elsewhere in this data book or from iliconix FaxBack. The CR60 series features guaranteed peak operating voltage minimum of 00 V with a typical of 80 V. The J00 series features 0 V minimum with a typical of 00 V. The lower current devices in both series provide excellent current regulation down to as little as V. iliconix Bias Resistor election All industry JFET part types exhibit a significant variation in I and V G(off) on min/max specifications and device-to-device variations. Using the simple source biasing current source as illustrated in Figure, the designer can graphically calculate the R which best fits the desired drain current I. Figure 7 plotting I versus V G over the military temperature range shows the resulting I for different values of R. The R lines are constructed by drawing the slope of the R desired value starting at the origin, eg. R = 2 k slope. Find a convenient point on the X Y axis to mark a V G I of 2 k such as V G =. V and I = 0.7 ma. Then, draw a straight line from this point to the origin. The intersection of this R line and the device I versus V G will be the operating I. In this example, the resulting I = 0.3 ma at T J = 2C. The intercepts of the T J = C and 2C show the minimal variation with temperature. Also note that JFETs have a I current where there is no change with temperature variation. To achieve this T C, the V G voltage (I x R ) is approximately: V G(0TC) V G(off) 0.6 V () 3

4 rain Current (ma) I Figure 7. T J = C R = 0.2 k 2C 0. k 2C V = 4 to 20 V 2N4339 max T/J202 (low end) k V G Gate-ource Voltage (V) 2 k k JFET Typical Transfer Characteristic 0 k 20 k 000 V = to 30 V T J = 2C except as noted I rain Current ( A) 00 T J = C 2C 2N/PN47A T47 Max 2N/PN47A T47 Min 2C 2N/PN48A T48 Max 2N/PN48A T48 Min 2N/PN49A T49 Max 2N/PN49A T49 Min R ource Resistance (k) Figure 8. ource Biased rain-current vs. ource Resistance 2 T J = C 2C 2C 2N4339 Max T/J202 Max V = 4 to 20 V T J = 2C except as noted rain Current (ma) 0. T/J20 Max 2N4338 Max T/J202 Min 2N4339 Min T/J20 2N4338 Min V I R R ource Resistance (k) Figure 9. JFET ource Biased rain-current vs. ource Resistance 4 iliconix

5 Choosing the Correct JFET for ource Biasing Each of the iliconix device data sheets include typical transfer curves that can be used as illustrated in Figure 7. everal popular devices are ideal for source biased current sources covering a few As to 20 ma. To aid the designer, the devices in Table have been plotted to show the drain current, I, versus the source resistance, R, in Figures 8, 9, and 0. Most plots include the likely worst case I variations for a particular R. For tighter current control, the JFET production lot can be divided into ranges with an appropriate resistor selection for each range. Table : ource Biasing evice Recommendations Practical Current Range I (ma) Through-Hole Plastic evice urface Mount evice Metal Can evice PN47A T47 2N47A PN48A T48 2N48A PN49A T49 2N49A J20 T20 2N J202 T202 2N J3 T3 2N J2 T2 2N C T J = 2C V = to 30 V T J = 2C except as noted I rain Current ( m A) Min 2N4393 T/J3 V 2C Mid 2N4393, T/J3 Max Min 2N4392, T/J2 Mid 2N4392, T/J2 R R ource Resistance (k) Figure 0. JFET ource Biased rain-current vs. ource Resistance iliconix