CA723, CA723C. Voltage Regulators Adjustable from 2V to 37V at Output Currents Up to 150mA without External Pass Transistors. Features.

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1 CA73, CA73C Data Sheet April 1999 File Number 788. Voltage Regulators Adjustable from V to 37V at Output Currents Up to 1mA without External Pass Transistors The CA73 and CA73C are silicon monolithic integrated circuits designed for service as voltage regulators at output voltages ranging from V to 37V at currents up to 1mA. Each type includes a temperature-compensated reference amplifier, an error amplifier, a power series pass transistor, and a current-limiting circuit. They also provide independently accessible inputs for adjustable current limiting and remote shutdown and, in addition, feature low standby current drain, low temperature drift, and high ripple rejection. The CA73 and CA73C may be used with positive and negative power supplies in a wide variety of series, shunt, switching, and floating regulator applications. They can provide regulation at load currents greater than 1mA and in excess of 1A with the use of suitable NPN or PNP external pass transistors. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. NO. CA73E - to 1 1 Ld PDIP E1.3 CA73T - to 1 1 Pin Can T1.C CA73CE to 7 1 Ld PDIP E1.3 Features Up to 1mA Output Current Positive and Negative Voltage Regulation Regulation in Excess of 1A with Suitable Pass Transistors Input and Output Short-Circuit Protection Load and Line Regulation % Direct Replacement for 73 and 73C Industry Types Adjustable Output Voltage V to 37V Applications Series and Shunt Voltage Regulator Floating Regulator Switching Voltage Regulator High-Current Voltage Regulator Temperature Controller Pinouts NC CA73 (PDIP) TOP VIEW - ERROR AMP + VOLT REF 1 13 FREQ 1 UNREG 11 V C 1 9 NC 7 8 NC - CA73C (CAN) TOP VIEW TAB 1 FREQ UNREG + ERROR AMP V C VOLT REF V O, (CASE INTERNALLY CONNECTED TO TERM ) 3-3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. or Copyright Intersil Corporation 1999

2 CA73, CA73C Functional Block Diagram TEMPERATURE- ENSATED ZENER UN ERTING V VOLT REF - ERROR REF AMP AMP + -ERTING FREQUENCY ENSATION ER SERIES PASS TRANSISTOR V C OUTPUT UN D1.V R1 Ω D3 R 1kΩ Q1 Q R3 kω Q3 Q C1 pf R7 Q R 1Ω D.V R8 kω R 1kΩ Q1 R9 3Ω Q7 R1 kω FIGURE 1. EQUIVALENT SCHEMATIC DIAGRAM OF THE CA73 AND CA73C Q9 -ERTING R 1kΩ Q11 Q1 Q13 R11 1Ω Q8 Q1 ERTING R1 1kΩ Q1 D V C Q1 FREQUENCY ENSATION 3-

3 CA73, CA73C Absolute Maximum Ratings DC Supply Voltage V (Between and Terminals) Pulse Voltage for ms Pulse Width (Between and Terminals) V Differential Input-Output Voltage V Differential Input Voltage Between Inverting and Noninverting Inputs ±V Between Noninverting Input and v Current From Zener Diode Terminal ( ) ma Operating Conditions Temperature Range o C to 1 o C Thermal Information Thermal Resistance (Typical, Note 1) θ JA ( o C/W) θ JC ( o C/W) PDIP Package N/A Metal Can Device Dissipation CA73T, Up to T A = o C mW CA73E, CA73CE, Up to T A = o C mW CA73T, Above T A = o C mW/ o C CA73E, CA73CE, Above T A = o C mW/ o C Maximum Storage Temperature Range o C to 1 o C Maximum Lead Temperature, During Soldering o C At a distance 1/1 ± 1/3 (1.9mm ±.79mm) from case for 1s Max CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θ JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications T A = o C, = V C = = 1V, =, = V, I L = 1mA, = 1pF, C REF =, =, Unless Otherwise Specified. Divider impedance R + R at noninverting input, Terminal = 1kΩ. (Figure ) CA73 CA73C PARAMETER TEST CONDITION MIN TYP MAX MIN TYP MAX UNITS DC CHARACTERISTICS Quiescent Regulator Current, I Q I L =, = 3V ma Input Voltage Range, V Output Voltage Range, V Differential Input-Output Voltage, V Reference Voltage, V Line Regulation (Note ) = 1V to V % = 1V to 1V % = 1V to 1V, T A = - o C to 1 o C = 1V to 1V, T A = o C to 7 o C % % Load Regulation (Note ) I L = 1mA to ma % I L = 1mA to ma, T A = - o C to 1 o C I L = 1mA to ma, T A = o C to 7 o C % % Output-Voltage Temperature Coefficient, T A = - o C to 1 o C %/ o C T A = o C to 7 o C %/ o C Ripple Rejection (Note 3) f = Hz to 1kHz db f = Hz to 1kHz, C REF = µf db Short Circuit Limiting Current, I LIM = 1Ω, = ma 3-

4 CA73, CA73C DC Electrical Specifications T A = o C, = V C = = 1V, =, = V, I L = 1mA, = 1pF, C REF =, =, Unless Otherwise Specified. Divider impedance R + R at noninverting input, Terminal = 1kΩ. (Figure ) (Continued) CA73 CA73C PARAMETER TEST CONDITION MIN TYP MAX MIN TYP MAX UNITS Equivalent Noise RMS Output Voltage, V N (Note 3) BW = 1Hz to 1kHz, C REF = BW = 1Hz to 1kHz, C REF = µf µv µv NOTES:. Line and load regulation specifications are given for condition of a constant chip temperature. For high dissipation condition, temperature drifts must be separately taken into account. 3. For C REF (See Figure ) Typical Performance Curves (CA73) MAXIMUM LOAD (ma) 1 1 MAX JUNCTION TEMP (T J ) = 1 o C THERMAL RESISTANCE = 1 o C/W QUIESCENT DISSIPATION (PQ) = mw (NO HEAT SINK) 1 o C 1 3 DIFFERENTIAL - OUTPUT VOLTAGE (V) LOAD REGULATION ( ) VOLTAGE ( ) = 1V RESISTANCE ( ) = AMBIENT TEMPERATURE (T A ) = o C - o C 1 o C 8 1 OUTPUT (ma) FIGURE. MAX LOAD vs DIFFERENTIAL - OUTPUT VOLTAGE FIGURE 3. LOAD REGULATION WITHOUT ING LOAD REGULATION ( ) o C AMBIENT TEMP (T A ) = o C VOLTAGE ( ) = 1V RESISTANCE ( ) = 1Ω 1 o C OUTPUT (ma) LOAD REGULATION ( ) VOLTAGE ( ) = 1V RESISTANCE ( ) = AMBIENT TEMPERATURE (T A ) = - o C 1 o C o C OUTPUT (ma) FIGURE. LOAD REGULATION WITH ING FIGURE. LOAD REGULATION WITH ING 3-

5 CA73, CA73C Typical Performance Curves (CA73) (Continued) OUTPUT VOLTAGE (V) o C o C AMBIENT TEMPERATURE (T A ) = - o C 8 1 OUTPUT (ma) VOLTAGE ( ) = 1V RESISTANCE ( ) = 1Ω QUIESCENT (ma) 3 1 OUTPUT VOLTAGE ( ) = REFERENCE VOLTAGE ( ) LOAD CIRCUIT (I L )= AMBIENT TEMPERATURE (T A ) = - o C 1 3 VOLTAGE (V) o C 1 o C FIGURE. ING CHARACTERISTICS FIGURE 7. QUIESCENT vs VOLTAGE MAXIMUM LOAD (ma) 1 1 MAX. JUNCTION TEMP. (T J ) = 1 o C THERMAL RESISTANCE = 1 o C/W QUIESCENT DISSIPATION (P Q ) = mw TO- STYLE PACKAGE WITH NO HEAT SINK 7 o C 1 3 DIFFERENTIAL - OUTPUT VOLTAGE (V) MAXIMUM LOAD (ma) 1 1 MAX. JUNCTION TEMP. (T J ) = 1 o C THERMAL RESISTANCE = 1 o C/W QUIESCENT DISSIPATION (P Q ) = mw DUAL - IN - LINE PLASTIC PACKAGE WITH NO HEAT SINK 7 o C 1 3 DIFFERENTIAL - OUTPUT VOLTAGE (V) FIGURE 8. MAX LOAD vs DIFFERENTIAL - OUTPUT VOLTAGE FIGURE 9. MAX LOAD vs DIFFERENTIAL - OUTPUT VOLTAGE FOR CA73CE LOAD REGULATION ( ) -.1 VOLTAGE ( ) = 1V RESISTANCE ( ) = o C 7 o C LOAD REGULATION ( ) -.1 VOLTAGE ( ) = 1V RESISTANCE ( ) = 1Ω o C 7 o C OUTPUT (ma) OUTPUT (ma) FIGURE 1. LOAD REGULATION WITHOUT ING FIGURE 11. LOAD REGULATION WITH ING 3-7

6 CA73, CA73C Typical Performance Curves (CA73) (Continued) OUTPUT VOLTAGE (V) o C o C OUTPUT (ma) VOLTAGE ( ) = 1V RESISTANCE ( ) = 1 OUTPUT VOLTAGE ( ) = REFERENCE VOLTAGE ( ) LOAD (IL) = FIGURE 1. ING CHARACTERISTICS FIGURE 13. QUIESCENT vs VOLTAGE Typical Performance Curves (CA73 and CA73C) QUIESCENT (ma) 3 1 o C 7 o C 1 3 VOLTAGE (V) LOAD REGULATION ( ) VOLTAGE ( ) = 1V LOAD (I L ) = I TO ma RESISTANCE ( ) = LINE REGULATION ( ).3..1 LOAD (I L ) = 1mA DIFFERENTIAL VOLTAGE ( VT) = 3V RESISTANCE () = DIFFERENTIAL - OUTPUT VOLTAGE (V) FIGURE 1. LOAD REGULATION vs DIFFERENTIAL - OUTPUT VOLTAGE DIFFERENTIAL - OUTPUT VOLTAGE (V) FIGURE 1. LINE REGULATION vs DIFFERENTIAL - OUTPUT VOLTAGE OUTPUT VOLTAGE DEVIATION (ma) VOLTAGE ( ) = 1V, LOAD (I L ) = ma RESISTANCE () = LOAD (I L ) OUTPUT VOLTAGE ( ) TIME (µs) LOAD DEVIATION (ma) ING VOLTAGE (V) ING VOLTAGE SHORT CIRCUIT ING WITH = Ω WITH = 1Ω JUNCTION TEMPERATURE ( o C) SHORT CIRCUIT ING (ma) FIGURE 1. LINE TRANSIENT RESPONSE FIGURE 17. ING CHARACTERISTIC vs JUNCTION TEMPERATURE 3-8

7 CA73, CA73C Typical Performance Curves (CA73 and CA73C) (Continued) OUTPUT VOLTAGE DEVIATION (ma) VOLTAGE ( ) OUTPUT VOLTAGE ( ) VOLTAGE ( ) = 1V - LOAD (I L ) = 1mA RESISTANCE - ( ) = TIME (µs) VOLTAGE DEVIATION (V) OUTPUT IMPEDANCE (W) VOLTAGE ( ) = 1V LOAD (I L ) = ma RESISTANCE ( ) = LOAD CAPACITANCE (C L ) = 1µF k 1k 1k 1M FREQUENCY (Hz) FIGURE 18. LOAD TRANSIENT RESPONSE FIGURE 19. OUTPUT IMPEDANCE vs FREQUENCY Typical Application Circuits VO VO C REF R 1pF OUTPUT 1pF OUTPUT 1V R Regulated Output Voltage V Line Regulation ( = 3V).mV Load Regulation ( I L = ma) 1.mV Note: = R For Minimum Temperature Drift + R FIGURE. LOW VOLTAGE REGULATOR CIRCUIT ( = V TO 7V) Line Regulation ( = 3V) 1.mV Load Regulation ( I L = ma).mv Note: = R For Minimum Temperature Drift + R May Be Eliminated For Minimum Component Count FIGURE 1. HIGH VOLTAGE REGULATOR CIRCUIT ( = 7V TO 37V) 3-9

8 CA73, CA73C Typical Application Circuits (Continued) R R kω V C R 1pF OUTPUT-1V R 1pF OUTPUT 1V Line Regulation ( = 3V) 1mV Load Regulation ( I L = 1mA) mv Note: For Applications Employing the TO- Style Package and Where Is Required, An External;.ener Diode Should be Connected in Series with (Terminal ). Line Regulation ( = 3V) 1.mV Load Regulation ( I L = 1A) 1mV FIGURE. NEGATIVE VOLTAGE REGULATOR CIRCUIT FIGURE 3. POSITIVE VOLTAGE REGULATOR CIRCUIT (WITH EXTERNAL NPN PASS TRANSISTOR) Ω V C N9 OR N18 OUTPUT V R C1.1µF OUTPUT V R.7kΩ.1µF 3Ω R.kΩ FIGURE. Line Regulation ( = 3V).mV Load Regulation ( I L = 1A) mv POSITIVE VOLTRAGE REGULATOR CIRCUIT (WITH EXTERNAL PNP PASS TRANSISTOR) Line Regulation ( V = 3V).mV Load Regulation ( I L = 1mA) 1mV Short Circuit Current ma FIGURE. FOLDBACK ING CIRCUIT 3-1

9 CA73, CA73C Typical Application Circuits (Continued) R D 1 1V SK3 R R 3.9kΩ.1µF = 8V TI N3 1Ω R 1kΩ R D 1 1V SK3 R V R O 1kΩ.1µF TI N11 Line Regulation ( V = V) 1mV Load Regulation ( I L = ma) mv OUTPUT-V NOTE: For applications employing the TO- Style Package and where is required, an external.v zener diode should be connected in series with (terminal ) FIGURE. POSITIVE FLOATING REGULATOR CIRCUIT OUTPUT-1V Line Regulation ( = V) 3mV Load Regulation ( I L =1mA) mv NOTE: For applications employing the TO- Style Package and where is required, an external.v zener diode should be connected in series with (terminal ) FIGURE 7. NEGATIVE FLOATING REGULATOR CIRCUIT NOTE R R 3 R C 1 kω TI.1µF N33.kΩ OUTPUT V CCSL LOGIC Line Regulation ( = 3V).mV Load Regulation ( I L = ma) 1.mV Short Circuit Current ma NOTE: 1. A current limiting transistor may be used for shutdown if current limiting is not required.. Add a diode if > 1V. FIGURE 8. REMOTE SHUTDOWN REGULATOR CIRCUIT WITH ING R C.µF 1Ω R 1Ω OUTPUT V Line Regulation ( = 1V).mV Load Regulation ( I L = 1mA) 1.mV NOTE: For applications employing the TO- Style Package and where is required, an external.v zener diode should be connected in series with (terminal ). FIGURE 9. SHUNT REGULATOR CIRCUIT All Intersil semiconductor products are manufactured, assembled and tested under ISO9 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site