CMOS 5 V/+5 V 4 Single SPDT Switches ADG619/ADG620

Transcription

1 a FEATURE (Max) On Resistance. (Max) On Resistance Flatness.7 V to 5.5 ingle upply.7 V to 5.5 V ual upply Rail-to-Rail Operation -Lead OT-3 Package, -Lead MOP Package Typical Power Consumption (<. W) TTL/CMO Compatible Inputs APPLICATION Automatic Test Equipment Power Routing Communication ystems ata Acquisition ystems ample-and-hold ystems Avionics Relay Replacement Battery-Powered ystems CMO 5 V/+5 V ingle PT witches AG9/AG FUNCTIONAL BLOCK IAGRAM AG9/AG WITCHE HOWN FOR A LOGIC PUT GENERAL ECRIPTION The AG9 and the AG are monolithic, CMO PT (single pole, double throw) switches. Each switch conducts equally well in both directions when on. The AG9/AG offer low on resistance of Ω, which is matched to within.7 Ω between channels. These switches also provide low power dissipation yet give high switching speeds. The AG9 exhibits break-before-make switching action, thus preventing momentary shorting when switching channels. The AG exhibits make-before-break action. The AG9/AG are available in an -lead OT-3 package and an -lead MOP package. Table I. Truth Table for the AG9/AG witch witch ON OFF OFF ON PROUCT HIGHLIGHT. Low On Resistance (R ON ) ( Ω typ).. ual ±.7 V to ±5.5 V or ingle.7 V to 5.5 upply. 3. Low Power issipation. CMO construction ensures low power dissipation.. Fast t ON /t OFF. 5. Tiny -Lead OT-3 Package and -Lead MOP Package. Information furnished by Analog evices is believed to be accurate and reliable. However, no responsibility is assumed by Analog evices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog evices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9, Norwood, MA -9, U..A. Tel: 7/ Fax: 7/ Analog evices, Inc. All rights reserved.

2 AG9/AG PECIFICATION UAL UPPLY ( = +5 V %, = 5 V %, GN = V. All specifications C to +5 C, unless otherwise noted.) B Version Parameter +5 C C to +5 C Unit Test Conditions/Comments ANALOG WITCH Analog ignal Range to V = +.5 V, =.5 V On Resistance (R ON ) Ω typ = ±.5 V, I = ma; Ω max Test Circuit On Resistance Match between Channels ( R ON ).7 Ω typ = ±.5 V, I = ma..35 Ω max On Resistance Flatness (R FLAT (ON) ).7. Ω typ = ±3.3 V, I = ma.5. Ω max LEAKAGE CURRENT = +5.5 V, = 5.5 V ource OFF Leakage I (OFF) ±. na typ = ±.5 V, V =.5 V; ±.5 ± na max Test Circuit Channel ON Leakage I, I (ON) ±. na typ = V = ±.5 V; Test Circuit 3 ±.5 ± na max IGITAL PUT Input High Voltage, V H. V min Input Low Voltage, V L. V max Input Current I L or I H.5 µa typ V = V L or V H ±. µa max C, igital Input Capacitance pf typ YNAMIC CHARACTERITIC AG9 t ON ns typ R L = 3 Ω, C L = 35 pf 55 ns max = 3.3 V; Test Circuit t OFF 5 ns typ R L = 3 Ω, C L = 35 pf 75 9 ns max = 3.3 V; Test Circuit Break-Before-Make Time elay, t BBM ns typ R L = 3 Ω, C L = 35 pf ns min = = 3.3 V; Test Circuit 5 AG t ON ns typ R L = 3 Ω, C L = 35 pf 5 5 ns max = 3.3 V; Test Circuit t OFF ns typ R L = 3 Ω, C L = 35 pf 33 ns max = 3.3 V; Test Circuit Make-Before-Break Time elay, t MBB ns typ R L = 3 Ω, C L = 35 pf ns min = V; Test Circuit Charge Injection pc typ = V, R = Ω, C L = nf; Test Circuit 7 Off Isolation 7 db typ R L = 5 Ω, C L = 5 pf, f = MHz; Test Circuit Channel-to-Channel Crosstalk 7 db typ R L = 5 Ω, C L = 5 pf, f = MHz; Test Circuit Bandwidth 3 db 9 MHz typ R L = 5 Ω, C L = 5 pf; Test Circuit 9 C (OFF) 5 pf typ f = MHz C, C (ON) 95 pf typ f = MHz POWER REQUIREMENT = +5.5 V, = 5.5 V I. µa typ igital Inputs = V or 5.5 V. µa max I. µa typ igital Inputs = V or 5.5 V. µa max NOTE Temperature range is as follows: B Version, C to +5 C. Guaranteed by design, not subject to production test. pecifications subject to change without notice. ±

3 AG9/AG GLE UPPLY ( = +5 V %, = V, GN = V. All specifications C to +5 C, unless otherwise noted.) B Version Parameter +5 C C to +5 C Unit Test Conditions/Comments ANALOG WITCH Analog ignal Range V to V =.5 V, = V On Resistance (R ON ) 7 Ω typ = V to.5 V, I = ma;.5 Ω max Test Circuit On Resistance Match between Channels ( R ON ). Ω typ = V to.5 V, I = ma..3 Ω max On Resistance Flatness (R FLAT (ON) ).5.5 Ω typ =.5 V to 3.3 V, I = ma Ω max LEAKAGE CURRENT = 5.5 V ource OFF Leakage I (OFF) ±. na typ = V/.5 V, V =.5 V/ V; ±.5 ± na max Test Circuit Channel ON Leakage I, I (ON) ±. na typ = V = V/.5 V; ±.5 ± na max Test Circuit 3 IGITAL PUT Input High Voltage, V H. V min Input Low Voltage, V L. V max Input Current I L or I H.5 µa typ V = V L or V H ±. µa max C, igital Input Capacitance pf typ YNAMIC CHARACTERITIC AG9 t ON ns typ R L = 3 Ω, C L = 35 pf ns max = 3.3 V; Test Circuit t OFF 5 ns typ R L = 3 Ω, C L = 35 pf 75 ns max = 3.3 V; Test Circuit Break-Before-Make Time elay, t BBM 7 ns typ R L = 3 Ω, C L = 35 pf, ns min = = 3.3 V; Test Circuit 5 AG t ON 5 ns typ R L = 3 Ω, C L = 35 pf 5 ns max = 3.3 V; Test Circuit t OFF ns typ R L = 3 Ω, C L = 35 pf 3 ns max = 3.3 V; Test Circuit Make-Before-Break Time elay, t MBB 7 ns typ R L = 3 Ω, C L = 35 pf ns min = 3.3 V; Test Circuit Charge Injection pc typ = V, R = Ω, C L = nf; Test Circuit 7 Off Isolation 7 db typ R L = 5 Ω, C L = 5 pf, f = MHz; Test Circuit Channel-to-Channel Crosstalk 7 db typ R L = 5 Ω, C L = 5 pf, f = MHz; Test Circuit Bandwidth 3 db 9 MHz typ R L = 5 Ω, C L = 5 pf; Test Circuit 9 C (OFF) 5 pf typ f = MHz C, C (ON) 95 pf typ f = MHz POWER REQUIREMENT = 5.5 V I. µa typ igital Inputs = V or 5.5 V. µa max NOTE Temperature range is as follows: B Version, C to +5 C. Guaranteed by design, not subject to production test. pecifications subject to change without notice. 3

4 AG9/AG ABOLUTE MAXIMUM RATG (T A = 5 C, unless otherwise noted.) to V to GN V to +.5 V to GN V to.5 V Analog Inputs V to +.3 V igital Inputs V to +.3 V or 3 ma, Whichever Occurs First Peak Current, or ma (Pulsed at ms, % uty Cycle max) Continuous Current, or ma Operating Temperature Range Industrial (B Version) C to +5 C torage Temperature Range C to +5 C Junction Temperature C MOP Package JA Thermal Impedance C/W JC Thermal Impedance C/W OT-3 Package JA Thermal Impedance C/W JC Thermal Impedance C/W Lead Temperature, oldering ( sec) C IR Reflow, Peak Temperature C NOTE tresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. Overvoltages at,, or will be clamped by internal diodes. Current should be limited to the maximum ratings given. P CONFIGURATION -Lead OT-3 (RT-) GN 3 AG9/ AG TOP VIEW 7 (Not to cale) 5 NC GN 3 NC = NO CONNECT -Lead MOP (RM-) AG9/ AG TOP VIEW (Not to cale) NC = NO CONNECT 7 5 NC ORERG GUIE Temperature Package Package Branding Model Range escription Option Information * AG9BRM C to +5 C Micro mall Outline Package (MOP) RM- VB AG9BRM-REEL C to +5 C Micro mall Outline Package (MOP) RM- VB AG9BRM-REEL7 C to +5 C Micro mall Outline Package (MOP) RM- VB AG9BRT-R C to +5 C Plastic urface Mount Package (OT-3) RT- VB AG9BRT-REEL C to +5 C Plastic urface Mount Package (OT-3) RT- VB AG9BRT-REEL7 C to +5 C Plastic urface Mount Package (OT-3) RT- VB AGBRM C to +5 C Micro mall Outline Package (MOP) RM- WB AGBRM-REEL C to +5 C Micro mall Outline Package (MOP) RM- WB AGBRM-REEL7 C to +5 C Micro mall Outline Package (MOP) RM- WB AGBRT-REEL C to +5 C Plastic urface Mount Package (OT-3) RT- WB AGBRT-REEL7 C to +5 C Plastic urface Mount Package (OT-3) RT- WB *Branding on OT-3 and MOP packages is limited to three characters due to space constraints. CAUTION E (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the AG9/AG features proprietary E protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper E precautions are recommended to avoid performance degradation or loss of functionality. WARNG! E ENITIVE EVICE

5 AG9/AG TERMOLOGY Mnemonic escription Most Positive Power upply Potential. Most Negative Power upply in a ual-upply Application. In single-supply applications, this should be tied to ground at the device. GN Ground ( V) Reference. I Positive upply Current. I Negative upply Current. ource Terminal. May be an input or output. rain Terminal. May be an input or output. Logic Control Input. R ON Ohmic Resistance between and. R ON On resistance match between any two channels, i.e., R ON Max R ON Min. R FLAT (ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. I (OFF) ource Leakage Current with the witch OFF. I, I (ON) Channel Leakage Current with the witch ON. V ( ) Analog Voltage on Terminals,. V L Maximum Input Voltage for Logic. V H Minimum Input Voltage for Logic. I L (I H ) Input Current of the igital Input. C (OFF) OFF witch ource Capacitance. C, C (ON) ON witch Capacitance. t ON elay between applying the digital control input and the output switching ON. t OFF elay between applying the digital control input and the output switching OFF. t MBB ON time is measured between the % points of both switches, when switching from one address state to another. t BBM OFF time or ON time is measured between the 9% points of both switches, when switching from one address state to another. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Crosstalk A measure of unwanted signal coupled through from one channel to another as a result of parasitic capacitance. Off Isolation A measure of unwanted signal coupling through an OFF switch. Bandwidth The frequency response of the ON switch. Insertion Loss The loss due to the on resistance of the switch. Typical Performance Characteristics ON REITANCE 7 5 3, =.5V, = 3V, = 3.3V, =.5V, = 5V ON REITANCE =.7V = 3V = 3.3V =.5V = 5V = V ON REITANCE 5 3 = +5V = 5V T A = +5 C T A = +5 C T A = C V, V TPC. On Resistance vs. V ( ) (ual upply) 3 5 V, V TPC. On Resistance vs. V ( ) (ingle upply) V, V TPC 3. On Resistance vs. V ( ) for ifferent Temperatures (ual upply) 5

6 AG9/AG ON REITANCE = 5V = V T A = +5 C T A = +5 C T A = C LEAKAGE CURRENT na = +5V = 5V V =.5V =.5V I (OFF) I, I (ON) LEAKAGE CURRENT na = 5V = V V =.5V/V = V/.5V I, I (ON) I (OFF) 3 5 V, V TPC. On Resistance vs. V ( ) for ifferent Temperatures (ingle upply) TEMPERATURE C TPC 5. Leakage Currents vs. Temperature (ual upply) TEMPERATURE C TPC. Leakage Currents vs. Temperature (ingle upply) CHARGE JECTION pc V 5V 5V V V TPC 7. Charge Injection vs. ource Voltage TIME ns t ON 5V V +5V 5V t OFF +5V 5V 5V V TEMPERATURE C TPC. t ON /t OFF Times vs. Temperature ALTERNATION db = +5V = 5V FREQUENCY MHz TPC 9. Off Isolation vs. Frequency ATTENUATION db = +5V = 5V. FREQUENCY MHz TPC. Crosstalk vs. Frequency ATTENUATION db = +5V = 5V. FREQUENCY MHz TPC. On Response vs. Frequency

7 AG9/AG TET CIRCUIT I V R ON = V/I I (OFF) I (OFF) V NC I (ON) A V Test Circuit. On Resistance Test Circuit. Off Leakage Test Circuit 3. On Leakage. F. F 5% 5% V GN R L 3 C L 35pF t ON 9% 9% t OFF Test Circuit. witching Times. F. F R L 3 C L 35pF V V V 5% 5% 9% 9% V GN t BBM t BBM Test Circuit 5. Break-Before-Make Time elay, t BBM (AG9 Only). F. F V V GN R L 3 C L 35pF R L 3 C L 35pF V V 5% 5% %V %V t MBB Test Circuit. Make-Before-Break Time elay, t MBB (AG Only) V R C L nf GN Q J = C L Test Circuit 7. Charge Injection 7

8 AG9/AG. F. F. F. F NETWORK ANALYZER NETWORK ANALYZER V GN 5 OFF IOLATION = LOG 5 R L 5 R 5 5 GN CHANNEL-TO-CHANNEL CROTALK = LOG V R 5 C7 /3(A) Test Circuit. Off Isolation Test Circuit. Channel-to-Channel Crosstalk. F. F NETWORK ANALYZER V GN 5 R L 5 ERTION LO = LOG WITH WITCH WITHOUT WITCH Test Circuit 9. Bandwidth OUTLE IMENION -Lead Mini mall Outline Package [MOP] (RM-) imensions shown in millimeters 3. BC -Lead mall Outline Transistor Package [OT-3] (RT-) imensions shown in millimeters.9 BC BC.9 BC. BC 3. BC.5. P.5 BC.3. COPLANARITY.. MAX EATG PLANE.3. COMPLIANT TO JEEC TANAR MO-7AA Revision History.. Updated OUTLE IMENION P.5 MAX BC.5 BC.5 MAX.. EATG PLANE COMPLIANT TO JEEC TANAR MO-7BA Location Page /3 ata heet changed from REV. to. Edits to PECIFICATION Updated ORERG GUIE