Transistors. NPN Bipolar Junction Transistor

Transcription

1 Transistors They are unidirectional current carrying devices with capability to control the current flowing through them The switch current can be controlled by either current or voltage ipolar Junction Transistors (JT) control current by current Field Effect Transistors (FET) control current by voltage They can be used either as switches or as amplifiers 1 NPN ipolar Junction Transistor One N-P (ase Collector) diode one P-N (ase Emitter) diode 1

2 PNP ipolar Junction Transistor One P-N (ase Collector) diode one N-P (ase Emitter) diode 3 NPN JT Current flow 4

3 JT α and β From the previous figure i E i + i C Define α i C / i E Define β i C / i Then β i C / (i E i C ) α /(1- α) Then i C α i E ; i (1-α) i E Typically β 100 for small signal JTs (JTs that handle low power) operating in active region (region where JTs work as amplifiers) 5 JT in Active egion Common Emitter(CE) Connection Called CE because emitter is common to both V and V CC 6 3

4 JT in Active egion () ase Emitter junction is forward biased ase Collector junction is reverse biased For a particular i, i C is independent of CC transistor is acting as current controlled current source (i C is controlled by i, and i C β i ) Since the base emitter junction is forward biased, from Shockley equation i C V E I CS exp 1 VT 7 Early Effect and Early Voltage As reverse-bias across collector-base junction increases, width of the collector-base depletion layer increases and width of the base decreases (base-width modulation). In a practical JT, output characteristics have a positive slope in forwardactive region; collector current is not independent of v CE. Early effect: When output characteristics are extrapolated back to point of zero i C, curves intersect (approximately) at a common point v CE -V A which lies between 15 V and 150 V. (V A is named the Early voltage) Simplified equations (including Early effect): i C I S exp v E V T 1+ v CE V A β F β FO 1+ v CE V A i I S exp v E β FO V T Chap

5 JT in Active egion (3) Normally the above equation is never used to calculate ic, i Since for all small signal transistors v E 0.7. It is only useful for deriving the small signal characteristics of the JT. For example, for the CE connection, i can be simply calculated as, V VE i or by drawing load line on the base emitter side 9 Deriving JT Operating points in Active egion An Example In the CE Transistor circuit shown earlier V 5V, kω, CC 1 kω, V CC 10V. Find I,I C,V CE,β and the transistor power dissipation using the characteristics as shown below y Applying KVL to the base emitter circuit i 100 μa I V V E 0 5V v E y using this equation along with the i / v E characteristics of the base emitter junction, I 40 μa 10 5

6 i C 10 ma 0 Deriving JT Operating points in Active egion An Example () y Applying KVL to the collector emitter circuit 100 μa 80 μa 60 μa 40 μa 0 μa 0V v CE VCC VCE IC CC y using this equation along with the i C / v CE characteristics of the base collector junction, i C 4 ma, V CE 6V I β I 4mA 40μA C 100 Transistor power dissipation V CE I C 4 mw We can also solve the problem without using the characteristics if β and V E values are known 11 JT in Cutoff egion Under this condition i 0 As a result i C becomes negligibly small oth base-emitter as well base-collector junctions may be reverse biased Under this condition the JT can be treated as an off switch 1 6

7 JT in Saturation egion Under this condition i C / i <βin active region oth base emitter as well as base collector junctions are forward biased V CE 0. V Under this condition the JT can be treated as an on switch 13 JT in Saturation egion () A JT can enter saturation in the following ways (refer to the CE circuit) For a particular value of i, if we keep on increasing CC For a particular value of CC, if we keep on increasing i For a particular value of i, if we replace the transistor with one with higher β 14 7

8 JT in Saturation egion Example 1 In the CE Transistor circuit shown earlier V 5V, kω, CC 10 kω, V CC 10V. Find I,I C,V CE,β and the transistor power dissipation using the characteristics as shown below Here even though I is still 40 μa; from the output characteristics, I C can be found to be only about 1mA and V CE 0.V( V C 0.5V or base collector junction is forward biased (how?)) i C 10 ma μa 80 μa 60 μa 40 μa 0 μa 0V v CE β I C / I 1mA/40 μa 5< JT in Saturation egion Example In the CE Transistor circuit shown earlier V 5V, 43 kω, CC 1 kω, V CC 10V. Find I,I C,V CE,β and the transistor power dissipation using the characteristics as shown below Here I is 100 μa from the input characteristics; I C can be found to be only about 9.5 ma from the output characteristics and V CE 0.5V( V C 0.V or base collector junction is forward biased (how?)) β I C / I 9.5 ma/100 μa 95 < 100 Transistor power dissipation V CE I C 4.7 mw Note: In this case the JT is not in very hard saturation 16 8

9 JT in Saturation egion Example () i 100 μa 0 5V v E i C 10 ma μa 80 μa 60 μa 40 μa 0 μa 0V v CE Input Characteristics Output Characteristics 17 JT in Saturation egion Example 3 In the CE Transistor circuit shown earlier V 5V, V E 0.7V kω, CC 1 kω, V CC 10V, β 400. Find I,I C,V CE, and the transistor power dissipation using the characteristics as shown below y Applying KVL to the base emitter circuit I V V E 40μA Then I C βi 400*40 μa μa and V CE V CC - CC* I C *1000-6V(?) ut V CE cannot become negative (since current can flow only from collector to emitter). Hence the transistor is in saturation 18 9

10 JT in Saturation egion Example 3() Hence V CE 0.V I C (10 0.) /1 9.8 ma Hence the operating β 9.8 ma / 40 μa JT Operating egions at a Glance (1) 0 10

11 JT Operating egions at a Glance () 1 JT Large-signal (DC) model 11

12 JT Q Point (ias Point) Q point means Quiescent or Operating point Very important for amplifiers because wrong Q point selection increases amplifier distortion Need to have a stable Q point, meaning the the operating point should not be sensitive to variation to temperature or JT β, which can vary widely 3 Four esistor bias Circuit for Stable Q Point y far best circuit for providing stable bias point 4 1

13 Analysis of 4 esistor ias Circuit V V TH Vcc + 1 TH Analysis of 4 esistor ias Circuit () Applying KVL to the base-emitter circuit of the Thevenized Equivalent form V -I -V E -I E E 0 (1) Since I E I + I C I + βi (1+ β)i () eplacing I E by (1+ β)i in (1), we get I V V E (3) + (1 + β) E If we design (1+ β) E >> (say (1+ β) E >> 100 ) Then I V V E (4) (1 + β) E 6 13

14 Analysis of 4 esistor ias Circuit (3) V V And I (for large β) E C IE (5) E Hence I C and I E become independent of β! Thus we can setup a Q-point independent of β which tends to vary widely even within transistors of identical part number (For example, β of NA, a NPN JT can vary between 75 and 35 for I C 1 ma and V CE 10V) 7 4 esistor ias Circuit -Example A NA is connected as shown with kω, 1 kω, C 3.3 kω, E 1 kω and V CC 30V. Assume V E 0.7V. Compute V CC and I C for β i)100 and ii)

15 4 esistor ias Circuit Example (1) I V V i) β 100 Vcc 30 * TH V 1 6.8*1 TH 0.87kΩ V VE + (1 + β) 1 E μA *1 I CQ βi 3.09 ma I EQ (1+ β)i 3.1 ma V CEQ V CC -I C C -I E E * *116.68V 9 4 esistor ias Circuit Example () I V i) β 300 Vcc VTH + 30 * V 1 6.8*1 TH 0.87kΩ V VE μA + (1 + β) *1 E I CQ 300I 3.13 ma I EQ (1+ β)i 3.14 ma V CEQ V CC -I C C -I E E * *116.53V 30 15

16 4 esistor ias Circuit Example (3) β 100 β 300 % Change VCEQ V V 0.9 % ICQ 3.09 ma 3.13 ma 1.9 % The above table shows that even with wide variation of β the bias points are very stable. 31 Four-esistor ias Network for JT V EQ V CC EQ V EQ EQ I + V E + E I E β F ,000 I ,000 (β F +1)I V I EQ V E 4V-0.7V EQ + (β F +1) E μa Ω I C β F I 01 μa I E (β F +1)I 04 μa V CE V CC C I C E I E α F V CE V CC C + F I C 4.3 V F. A. region correct - Q-point is (01 μa, 4.3 V) 3 16

17 Four-esistor ias Network for JT (cont.) All calculated currents > 0, V C V E - V CE V Hence, base-collector junction V CE V CC is reverse-biased, C + F α and assumption of forward-active region F operation is correct. The two points needed to plot the load line are (0, 1 V) and (314 μa, 0). Load-line for the circuit esulting is: load line is plotted on I C 1 38,00 I C common-emitter output characteristics. I.7 μa, intersection of corresponding characteristic with load line gives Q-point. 33 Four-esistor ias Network for JT: Design Objectives We know that I E V EQ V E EQ I E V EQ V E E for EQ I << (V EQ V E ) This implies that I << I, so that I 1 I. So base current doesn t disturb voltage divider action. Thus, Q-point is independent of base current as well as current gain. Also, V EQ is designed to be large enough that small variations in the assumed value of V E won t affect I E. Current in base voltage divider network is limited by choosing I I C /5. This ensures that power dissipation in bias resistors is < 17 % of total quiescent power consumed by circuit and I >> I for β >

18 Four-esistor ias Network for JT: Design Guidelines Choose Thévenin equivalent base voltage V CC 4 V V CC EQ Select 1 to set I 1 9I. Select to set I 10I. 1 V EQ 9 I V CC V EQ 10 I E is determined by V EQ and desired I C. E V EQ V E I C C is determined by desired V CE. C V CC V CE I C E 35 Four-esistor ias Network for JT: Example Problem: Design 4-resistor bias circuit with given parameters. Given data: I C 750 μa, β F 100, V CC 15 V, V CE 5 V Assumptions: Forward-active operation region, V E 0.7 V Analysis: Divide (V CC - V CE ) equally between E and C. Thus, V E 5 V and V C 10 V C V V CC C 6.67 kω I C E V E 6.60 kω I E V V E + V E 5.7 V I I C β F 7.5 μa I 10I 75.0 μa I 1 9I 67.5 μa 1 V 9I 84.4 kω V CC V 10I 14 kω 36 18

19 Two-esistor ias Network for JT: Example Problem: Find Q-point for pnp transistor in -resistor bias circuit with given parameters. Given data: β F 50, V CC 9 V Assumptions: Forward-active operation region, V E 0.7 V Analysis: 9 V E +18,000 I (I C + I ) 9 V E +18,000 I (51)I 9V 0.7V I 10 μa 69,000 Ω I C 50 I 6.01 ma V EC (I C + I ).88 V V C.18 V Forward-active region operation is correct Q-point is : (6.01 ma,.88 V) 37 19