Lecture 30: Biasing MOSFET Amplifiers. MOSFET Current Mirrors.

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1 Whites, EE 320 Lecture 30 Page 1 of 8 Lecture 30: Biasing MOSFET Amplifiers. MOSFET Current Mirrors. There are two different environments in which MOSFET amplifiers are found, (1) discrete circuits and (2) integrated circuits (ICs). The methods of biasing transistor amplifiers are different in these two environments. Why? Primarily because it s expensive to fabricate resistors (and large capacitors) on ICs. Of course, this is not a problem for discrete component circuits. We will discuss these two environments separately. Biasing iscrete MOSFET Amplifier Circuits The methods we can use here are virtually identical to the BJT amplifier circuits we saw in Chapter 5. A few of these biasing topologies are: (Fig. 4.30d) 2009 Keith W. Whites

2 Whites, EE 320 Lecture 30 Page 2 of 8 (Fig. 4.32) (Fig. 4.33a) Example N30.1. esign the MOSFET amplifier below so that I = 1 ma and allow for a drain voltage swing of ± 2 V. The amplifier is to present a 1-MΩ input resistance to a capacitively coupled input signal. The transistor has k n W L= 0.5 ma/v 2 and V t = 2 V. I = 1 ma v o v i

3 Whites, EE 320 Lecture 30 Page 3 of 8 We can see directly from this circuit that at C, V G = 0. Recall that for operation in the saturation mode VG Vt (with V GS > 0). Now, for ± 2-V swing in v o and large AC gain, we want R to be large. Hence, let s choose V = 0 (since V t = 2 V). Then for this ± 2-V swing in v o VG = 0 2= 2 V< V min t and VG = 0+ 2= 2 V= V max t Because of these results, the MOSFET stays in saturation. Consequently, with V = 0 V V 10 0 R 1 ma 1 ma 10 = = = kω For a saturated MOSFET 1 W 3 I = k n VGS Vt = VGS 2 2 L 2 For I = 1 ma ( VGS 2) = 4 or V GS =± 2+ 2= +4 V or 0 V. ( ) ( ) 2 2 With V G = 0 and V GS = 4 V then V S = 4 V. Hence, 4 ( 10) R S = = 6 kω 1 ma Lastly, for a 1-MΩ AC input resistance, then referring to the input portion of the small-signal model

4 Whites, EE 320 Lecture 30 Page 4 of 8 v gs g v m gs v o we see that R in = R R = 1 MΩ G G Biasing IC MOSFET Amplifiers. Current Mirrors. For MOSFET amplifier biasing in ICs, C current sources are usually used. As discussed in Lecture 17, golden currents are produced using sophisticated multi-component circuits. Then current mirroring (aka current steering) circuits are used to replicate this golden current to provide C biasing currents at different points in the IC. The basic MOSFET current mirror is shown in Fig. 4.33b for NMOS. (This is basically the same circuit we saw with the BJT current mirror in Lecture 17.)

5 Whites, EE 320 Lecture 30 Page 5 of 8 (Fig. 4.33b) Q 1 has the drain and gate terminals connected together. This forces Q 1 to operate in the saturation mode in this particular circuit if I 1 0. In this mode 1 W1 I ( ) 2 1 = k n1 VGS Vt1 (4.50),(1) 2 L1 With a zero gate current, IREF = I 1 (2) where we can easily see from the above circuit that V VGS ( VSS) IREF = (4.51),(3) R Now, we ll assume the two MOSFETs in the circuit have the same V GS. Consequently, the drain current in the second transistor is 1 W2 I ( ) 2 2 = k n2 VGS Vt2 (4) 2 L 2

6 Whites, EE 320 Lecture 30 Page 6 of 8 If these two transistors are perfectly matched but perhaps fabricated with different channel dimensions, then k n1 = k n2, and Vt1 = Vt2 so that we see by comparing (1) and (4) that W2 L2 W2 L2 I = 2 I 1 IREF W L = W L (4.53),(5) In this NMOS current mirror shown above, Q 2 acts as a current sink since it pulls current IO = I 2 from the load, which is the amplifier circuit of Fig. 4.33a in this case. In PMOS this current mirror circuit is constructed as V Q 1 Q 2 R 0 I REF I = I O 2 To amplifier circuit Here Q 2 acts as a current source since it pushes current IO = I 2 into the load. Example N30.2. esign an NMOS current mirror with V = 5 V, V SS = 0, and I REF = 100 μa. For the matched transistors L = 10 μm, W = 100 μm, V = 1 V, and k = 20 μa/v 2. t n

7 Whites, EE 320 Lecture 30 Page 7 of 8 Referring to the NMOS current mirror circuit in Fig. 4.33b above, notice that the drain of Q 1 is connected to its gate so that V G1 = 0, which is less than V t. This means Q 1 is operating in the saturation mode (or is possibly cutoff). Assuming operation in saturation, 1 W I ( ) 2 1 = IREF = k n VGS Vt 2 L = V GS ( ) 2 For REF I = 100 μa 100 = 10 10( V 1) 2 GS or =± 1+ 1= 2 V or 0 V V GS Now, by KVL V = IREFR+ VGS With V GS = 2 V then GS 5 2 R V V = = = 30 kω I 100 μa REF Here are a few additional questions based on this design: What is the lowest possible value for VO = V2 and still have a functioning current mirror? As with Q 1, the transistor Q 2 must also operate in saturation if it s going to supply a constant current.

8 Whites, EE 320 Lecture 30 Page 8 of 8 Hence VG2 Vt VG2 V2 Vt VO = V2 VG2 Vt or VO VGS Vt = 2 1= 1V Therefore, V = 1 V min O 7 Imagine that VA = 10 L. (Notice that V A is proportional to the channel length, which is commonplace.) What is r o? 7 6 V A = = 100 V VA 100 V r o = = = 1 MΩ I 100 μa O What is change in the output current I O if V O changes by 3 V? ΔVO 3 V ΔI O = = = 3 μa r 1 MΩ o