Two-Phase Clocking Scheme for Low-Power and High- Speed VLSI

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1 International Journal of Advances in Engineering Science and Technology 225 and ISSN: Two-Phase Clocking Scheme for Low-Power and High- Speed VLSI Rajalaxmi Das, Ghanshyam Kumar Singh & Ram Mohan Mehra Department of Electronics and Communication Engineering School of Engineering & Technology Sharda University, Knowledge Park-III, Greater Noida, (UP), India - Abstract: Synchronisation is very important in every digital circuit. For accuracy, high speed, with consistent output, without any critical race and also for low power purpose synchronisation is very much essential. Pipelining is a key element for high-performance design and is a straightforward technique for synchronous systems. Here Xilinx tool is used because it is so easier and implemented with VHDL. Two phase clocking scheme can be obtained from single phase by pipeline technique. This paper present a low-power and high speed flip-flop and latch combination performing the same operation. Here Flipflop and latch combination have been implemented. As flip-flop is edge trigger is faster in speed and latch is labelled triggered it act as low power device. Latch-based designs have small die size and are more successful in high-speed designs. For low power operation, CMOS chosen, CMOS logic dissipates less power than NMOS. So it is very useful for low power and high speed purpose. Keywords: Two phase clocking scheme, Flip-flop, Latch I. INTRODUCTION The major concerns of the VLSI designer were area, performance, cost and reliability; power considerations were mostly of only secondary importance. In recent years, however, this has begun to change and, increasingly, power is being given comparable weight to area and speed. Portable computing and communication devices demand high-speed computation and complex functionality with low power consumption [1-5]. For VLSI circuit synchronous design approaches is most essential, so two phase clock signal should be taken account rather than the single phase, an efficient clocking scheme is always important for designing high performance systems [6-7]. The two-phase clocking scheme is motivated from a low power point of view. C 2 MOS-latches are good carrier for low power. In order to obtain continuous clock signal from the C 2 MOS-latches, the non-overlapping two-phase clocking scheme has to be appointed using pipeline technique of two blocks is a combination of latch and flip-flop which provide efficient low power and high speed application [8-11]. We present two phase clocking by implementing pipeline section, which results non-overlapping clock signal, avoid circuit delays, clock period, and clock width for the correct operation of the circuit. TPCS (two phase clocking signal) also avoid multi-stepping or race condition in the circuit. By using two phase clock signal the circuit will be clocked circuit or synchronise circuit. Pipeline technique enhances the two phase system and the application of flip-flop provides high performance and faster speed. II. DESIGNING FOR LOW POWER A. True Single Phase The design using a single-phase clocking scheme, there are a number of tight constraints that have to be met with respect to circuit delays, clock period, and clock width for the correct operation of the circuit. Clock skew is a serious problem when a number of chips are put together to form a total system. But even within a single large and complex chip, the effects due to skew must be analyzed thoroughly to

2 IJAEST, Volume 2, Number 2 Rajalaxmi Das et al. avoid faulty circuit operation. dynamic clocking schemes such as the NORA (NO Race) scheme using true two-phase clock signals Ø1, andø2 have been used to avoid race problems caused by clock skew, the imperfect synchronization between a clock signal and its inverse. This scheme requires some constraints on logic combination, such as clock edges of short duration that increases the demand on both the clock generation circuitry and the interconnections that distribute the clock signals across the chip. As a dynamic CMOS technique, NORA is sensitive to charge sharing and leakage. These NORA, clock skew can be avoided by using two-phase clock signal. Figure-1: Non overlapping pseudo two phase clock, Figure-2: Wave form with dead time Figure: 3(a) Two phase signal from single phase (b) Clock Period of two phase The block diagram of the clock generator used the two non-overlapping clock-phases, Ø1 and Ø2, are designed from a single-phase clock, running at a double clock rate. A divide-by-two circuit halves the clock rate and produces two internal clock signals, and its inverse. Finally, the two clock phases Ø1 and Ø2 are obtained from two simple AND-gates. Systems using C 2 MOS circuits of both static and dynamic nature involve a clocking strategy for the purpose of system timing. The original clocking strategy was the clocked CMOS logic (C 2 MOS) which uses a non-overlapping pseudo two phase clock. This system is very sensitive to clock skew that is one clock can experience more propagation delay than the other which has become a dominant problem in current high performance designs and results in difficulties in increasing circuit speed. B. Sequential logic application An alternative implementation of the flip-flop is that makes use of a "clocked inverter. In which the clocked transistors are placed between the inverter and supply rails. Applying this clocking strategy to the flip-flops used in the pseudo 2-phase clocking, the structure in is constructed. A "clock race" condition encountered in the pseudo 2-phase latch can arise in this structure. This is, of course, an accentuated case of pseudo &phase clock skew mentioned previously. Considering Ø delayed from Ø, here the first clocked CMOS ( clocked inverter" ) n-transistor can be turned on at the same time as the second clocked inverter" n-transistor will be turn off.

3 Two-Phase Clocking Scheme for Low-Power and High-Speed VLSI 227 Figure: 4 (a &b) Two phase flip flop and latch This combines N-P sections of domino logic with a C 2 MOS latch as the output stage. We can build Ø blocks, which resolve during Ø, and Ø blocks. Cascading these N-P blocks is achieved the structure in Fig. Which yields a pipelined structure in which Ø sections are precharged and Ø sections are evaluated when Ø = 0,Ø =1. Information to Ø sections is held constant by the clocked CMOS latch in the output of Ø sections. When Ø = 1, Ø = 0.Now Ø sections are evaluated and Ø section are precharged. Often it is desired to mix N-P dynamic sections with static logic otherwise connect N-P sections with domino sections. Figure: 5 N-P CMOS Ø logic If this is done, two problems must be avoided. Firstly, self-contained sections must be internally race free. Secondly, when different sections are cascaded to form pipelined systems, clock skew should result zero deleterious effects. We will examine some rules that have been proposed to deal with both problems. In the case of internal races, the basic rules for dynamic domino must be followed, During pre-charge, logic blocks must be switched off. During evaluation, the internal inputs can make only one transition. Pipeline is a technique used in the design to increase their instruction throughput that is the number of instructions that can be executed in a unit of time.

4 IJAEST, Volume 2, Number 2 Rajalaxmi Das et al. Figure: 6 (a) N-P CMOS Ø logic (b) Precharge and evaluation stage In VLSI technology, dynamic clocking scheme using true two-phase clock signals Ø1, andø2 have been used to avoid race problems caused by clock skew. There are several benefits with this technique such as the elimination of skew due to different clock phases and the clock signal being generated off - chip, which implies significant savings in chip area and power consumption. The generation and distribution of the clock is likely not to be a factor on maximum sustainable clock frequency. C.NORA Dynamic circuit The NORA(NO-RACE) RACE) dynamic CMOS technique uses a true non-overlapping overlapping two-phase-clock signal Ø and Ø', and can avoid race problems caused by clock skew. This technique extends the concept of the C 2 MOS latch to support the effective implementation of pipelined circuits by adding a precharge and an evaluation stages. NORA dynamic CMOS technique can reach higher clock rates than the C 2 MOS technique since there is no dead time and no skew problem. Figure.7 (a) NORA(NO-RACE) RACE) dynamic CMOS technique (b) Wave form for NORA D. Pipeline technique The Pipeline is a technique used in the design to increase their instruction throughput that is the number of instructions that can be executed in a unit of time. Inverting a single clock can lead to skew problems. Employ two non-overlapping overlapping clocks for master and slave sections of a flip-flop flop also, use two phases for alternating pipeline stages. High-performance digital system design is the use of pipelining. Figure: 8(a) Block diagram for Pipeline section Figure: 8(b) RTL of complete pipeline block diagram

5 Two-Phase Clocking Scheme for Low-Power and High-Speed VLSI 229 III. RESULTS & DISCUSSIONS: Pipelining is a key element for high-performance design and is a straightforward technique for synchronous systems. Complex function blocks are subdivided into smaller blocks, registers are inserted to separate them, and the global clock is applied to all registers. The schematic diagram of pipeline is shown in Fig-9 and the simulation waveforms are shown in Fig-10. In digital sequential circuit synchronisation is used in the vast majority. The sequential circuit included all resistors, flip-flop, latches and memory elements, In this study Flip-flop and latch have been implemented as a combination of one block, two blocks & many blocks. This thesis is related to lowpower and high speed flip-flop and latch combination will performing the same operation. As flip-flop is edge trigger is faster in speed and latch is labelled triggered it act as low power device. Latch-based designs have small die size and are more successful in high-speed designs. For low power operation, CMOS chosen instead of NMOS. CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates power only when switching ("dynamic power"). On a typical ASIC in a modern 90 nanometre process, switching the output might take 120 picoseconds, and happens once every ten nanoseconds CMOS switches have a single-pin control interface that enables maximum circuit layout efficiency. Here two phase clocking technology is implemented with Clocked CMOS Which prevents from Glitches, unwanted hazard. The implementation of NORA dynamic CMOS technique uses a true nonoverlapping two-phase-clock Signal Ø and Ø', and can avoid race problems caused by clock skew. NORA dynamic CMOS technique can provide higher clock rates than the C 2 MOS technique as there is very negligible dead time and no skew problem. Figure: 9 Schematic diagram of pipeline

6 IJAEST, Volume 2, Number 2 Rajalaxmi Das et al. Figure: 10 Simulation wave form IV. CONCLUSION In this paper true single phase clocking is modified to two phase clocking by implementing pipeline section, which results non-overlapping clock signal, avoid circuit delays, clock period, and clock width for the correct operation of the circuit. TPCS also avoid multi-stepping or race condition in the circuit. By using two phase clock signal the circuit will be clocked circuit or synchronise circuit. Pipeline technique enhances the two phase system. The application of flip-flop provides high performance and faster speed. REFERENCES [1] Takahashi, Y.; Zhongyu Luo; Sekine, T.; Nayan, N.A.; Yokoyama, M. "2PCDAL: Two-phase clocking dual-rail adiabatic logic", Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on, On page(s): [2] Chanda, M.; Kundu, S.; Adak, I.; Dandapat, A.; Rahaman, H. "Design and analysis of tree-multiplier using single-clocked energy efficient adiabatic Logic", Students' Technology Symposium (TechSym), 2011 IEEE, On page(s): [3] Gong, C.-S.A.; Kai-Wen Yao; Muh-Tian Shiue; Yin Chang "Adiabatic technique for biomedical applications", Intelligent Signal Processing and Communications Systems (ISPACS), 2012 International Symposium on, On page(s): [4] Anuar, N.; Takahashi, Y.; Sekine, T. "Fundamental logics based on two phase clocked adiabatic static CMOS logic", Electronics, Circuits, and Systems, ICECS th IEEE International Conference on, On page(s): [5] Anuar, N.; Takahashi, Y.; Sekine, T. "XOR evaluation for 4 4-bit array two-phase clocked adiabatic static CMOS logic multiplier", Circuits and Systems (MWSCAS), rd IEEE International Midwest Symposium on, On page(s): [6] Takahashi, Y.; Fukuta, Y.; Sekine, T.; Yokoyama, M. "2PADCL: Two Phase drive Adiabatic Dynamic CMOS Logic", Circuits and Systems, APCCAS IEEE Asia Pacific Conference on, On page(s): [7] Nayan, Nazrul Anuar; Takahashi, Yasuhiro; Sekine, Toshikazu "LSI implementation of a low-power 4Ã 4-bit array twophase clocked adiabatic static CMOS logic multiplier", Microelectronics Journal,Volume.43, Issue.4, pp.244, 2012, ISSN: , [8] Anuar, Nazrul; Takahashi, Yasuhiro; Sekine, Toshikazu "Two Phase Clocked Adiabatic Static CMOS Logic and its Logic Family", JSTS Journal of Semiconductor Technology and Science,Volume.10, Issue.1, pp.1, 2010, ISSN: , [9] Hong Kong Bai-Sun Kong'. Young-Hyun Jun' and Kwyro Lee A TRUE SINGLE-PHASE CLOCKING SCHEME FOR LOW- POWER AND HIGH-SPEED VLSI, IEEE International Symposium on Circuits and Systems, June 9-12,1997 [10] ZHANG, Yimeng; OKAMURA, Leona; YOSHIHARA, Tsutomu "An Energy Efficiency 4-bit Multiplier with Two-Phase Non-overlap Clock Driven Charge Recovery Logic", IEICE Transactions on Electronics, Volume.e94-c, Issue.4, pp.605, 2011, ISSN: , [11] Bargagli-Stoffi, A.; Iannaccone, G.; Di Pascoli, S.; Amirante, E.; Schmitt-Landsiedel, D. "Four-phase power clock generator for adiabatic logic circuits", Electronics Letters, Volume.38, Issue.14, pp.689, 2002, ISSN:

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