Lecture 11. Registers and Counters

Transcription

1 Logic Design Lecture 11. Registers and Counters Prof. Hyung Chul Park & Seung Eun Lee

2 12.1 Registers and Register Transfers Register- a collection of binary storage elements In theory, a register is sequential logic which can be defined by a state table More often, think of a register as storing a vector of binary values Frequently used to perform simple data storage and data movement and processing operations 2

3 12.1 Registers and Register Transfers 4-bit D flip-flop using gated clock 3

4 12.1 Registers and Register Transfers 4-bit D flip-flop registers with data, load, clear, and clock inputs Load is a frequent name for the signal that controls register storage and loading Load=1: Load the values on the data inputs Load=0: Hold the values in the register 4

5 12.1 Registers and Register Transfers With clock enable 5

6 12.1 Registers and Register Transfers Transferring data between registers is a common operation in digital systems 6

7 12.1 Registers and Register Transfers Logic diagram for 8-bit register with tri-state output 7

8 12.1 Registers and Register Transfers Data transfer using a tri-state bus 8

9 12.1 Registers and Register Transfers Multiplexer based transfers K1: R0 <-R1 K2(K1) : R0-<R2 Load R2 K 2 K 1 Load n n S 0 MUX 1 n Load R0 R1 9

10 12.1 Registers and Register Transfers Parallel adder with accumulator 10

11 12.1 Registers and Register Transfers Adder cell with multiplexer 11

12 12.2 Shift Registers Shift registers move data within the register toward its MSB or LSB position In the simplest case, the shift register is simply a set of D flip-flops connected in a row In DQ A B C Out DQ DQ DQ CP Data input, In, is called a serial input Data output, Out, is often called the serial output The vector (A, B, C, Out) is called the parallel output 12

13 12.2 Shift Registers The behavior of the serial shift register In A B C Out DQ DQ DQ DQ CP CP In A B C Out T0 0???? T1 1 0??? T ?? T ? T4 1 T5 1 T6 1 13

14 Right shift register 12.2 Shift Registers 14

15 12.2 Shift Registers 8-bit serial-in, serial-out shift register 15

16 12.2 Shift Registers Typical timing diagram for shift register 16

17 12.2 Shift Registers Shift register with inverted feedback (Johnson counter) 17

18 12.3 Design of Binary Counters An N-bit binary counter is a sequential arithmetic circuit with clock, reset, and an N-bit output Increment output on each clock edge Used to count cycles via numbers For example: 000, 001, 010, 011, 100, 101, 110, 111, 000, 001 Counters are used in many digital systems Digital clock displays Program counter (PC) register is used in computers to keep track of the current instruction CPU is executing 18

19 12.3 Design of Binary Counters A binary counter using three T F/F Counting sequence CBA:

20 12.3 Design of Binary Counters State Table for binary counter 20

21 12.3 Design of Binary Counters K-map for the binary counter TA=1, TB=A, TC=AB 21

22 12.3 Design of Binary Counters Binary counter with D F/F 22

23 12.3 Design of Binary Counters D D D A B C A B C A BA B A B A C BA CB CA C BA C( BA) C BA 23

24 12.3 Design of Binary Counters State graph and table for up-down counter When U=1, Up counting When D=1, Down counting 24

25 12.3 Design of Binary Counters Implementation using D F/F 25

26 12.3 Design of Binary Counters Corresponding eq. When U=0 and D=1 26 ) ( ) ( ) ( DB A UBA C C D DA UA B B D D U A A D C B A 0) change state when ( 0) change state when ( change state every clock cycle) ( 1 A B C B A C C D A B A B B D A A A A D C B A

27 12.3 Design of Binary Counters Loadable counter with count enable 27

28 12.3 Design of Binary Counters Loadable counter circuit 28

29 12.4 Counters for Other Sequences The sequence of states of a counter is not in straight binary order 29

30 12.4 Counters for Other Sequences Next state K-maps 30

31 12.4 Counters for Other Sequences Derivation of T inputs (use T F/F) 31

32 12.4 Counters for Other Sequences Counter using T F/F 32

33 12.4 Counters for Other Sequences Timing diagram 33

34 12.4 Counters for Other Sequences When CBA=001 34

35 12.4 Counters for Other Sequences Summary: 1.Form a state table which gives the next F/F states for each combination of present F/F states. 2.Plot the next-state maps from the table. 3.Plot a T input map for each F/F. 4.Find the T input equations from the maps and realize the circuit. 35

36 12.4 Counters for Other Sequences Counter using D F/F D C C B D B B C BA D A A CA BA A ( C B) 36

37 12.4 Counters for Other Sequences Counter using D F/F D C C B D B B C BA D A A A ( C B) 37

38 12.5 Counter Design Using S-R and J-K Flip-Flops S-R F/F inputs 38

39 12.5 Counter Design Using S-R and J-K Flip-Flops S-R F/F excitation table 39

40 12.5 Counter Design Using S-R and J-K Flip-Flops Using S-R F/F 40

41 12.5 Counter Design Using S-R and J-K Flip-Flops Using S-R F/F 41

42 12.5 Counter Design Using S-R and J-K Flip-Flops J-K F/F inputs 42

43 12.5 Counter Design Using S-R and J-K Flip-Flops J-K F/F Excitation Table 43

44 12.5 Counter Design Using S-R and J-K Flip-Flops Using J-K F/F 44

45 12.5 Counter Design Using S-R and J-K Flip-Flops Using J-K F/F 45